09:16 <qookie[m]> hi, I don't know if this is a misunderstanding on my part, but I am running into inter-clock path setup timing violations when using AsyncFIFO{,Buffered} to move data between different clock domains. for context: I'm targeting a series-7 FPGA and using Vivado for synth and impl, the FIFO is small enough to be implemented as LUTRAM, the two clocks come from two MMCMs and don't have an integer ratio (crossing from a 160MHz SoC clock

09:16 <qookie[m]> to a 65MHz pixel clock)

09:42 <whitequark> if they don't have an integer ratio you need to treat them as fully async

09:42 <whitequark> otherwise you'll always have setup violations. use set_async_groups constraint

12:10 <qookie[m]> thanks, that did the trick, i'm a bit surprised it tries to reason about them as being synchronous in the first place

12:13 <qookie[m]> also on the topic of adding constraints, am i missing something or is the only way to add them is to override toolchain_prepare in the platform and put add_constraints=... there