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<whitequark>
working on a revD-compatible firmware
<whitequark>
i decided to bite the bullet and do a complete rewrite instead of doing it incrementally
<whitequark>
rolling up several major changes into one update
<whitequark>
risky, but doing them one by one is going to take forever, and they're mostly interdependent which explodes the amount of work
<whitequark>
the changes are: revD support, bitstream submission via EP2 instead of EP0 (required for revD), performance fix for Windows (not using non-first USB device configuration), using a packet based protocol over EP1IN/OUT that is network-transparent, (possibly) a more efficient way of interacting with the I2C bus
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<josHua[m]1>
this is the COBS packetization mechanism previously proposed?
<whitequark>
no, EP1 is FX2-only
<whitequark>
this is just ditching the USB-oriented management protocol with something much more normal
<whitequark>
it also allows the device to send data to the host of its own accord, which is important for various alerting functions
<whitequark>
which we keep adding but not properly integrating
<whitequark>
so, control_{read,write} is replaced with uh, send_raw_packet(x:bytes) and on_recv_raw_packet(x:bytes)
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<whitequark>
and then you implement it the way you'd implement a TLV-based networking thing
<whitequark>
nobody moves or i add another storage class specifier!!
* WilfriedWonkaKla
moves
<whitequark>
__sfr24
<WilfriedWonkaKla>
😁
<whitequark>
i've never written so many gotos
<whitequark>
i've also occasionally made use of the little known C feature that case labels don't have to be lexically directly within switch braces
<whitequark>
also switch() x with no {} is legal
<whitequark>
sooo you could do something like thinks switch(x) do { case A: continue; case B: ...; } while (0) or something
<mkj[m]>
hooray
<whitequark>
it's really difficult to find a use for the second pattern so it's only of academic interest
<whitequark>
mainly you can use it to jump in the middle of a conditional
<whitequark>
switch (x) case A: if (something) { ... case B: ... }
<whitequark>
nobody sane should write code like this, but sdcc doesn't do any nonlocal optimizations, so you actually have to imagine the CFG it comes up with
<whitequark>
what is a cpu? a miserable little pile of registers
<whitequark>
and complex microarchitectural conditions. mostly the latter, really
<whitequark>
anyhow, the new firmware now lets you configure the DACs
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<tpw_rules>
what does c give you at this point
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<whitequark>
uh
<whitequark>
what do you mean?
<tpw_rules>
on an 8051 through sdcc. why not just write the asm
<josHua[m]1>
hm can SDCC TCO set_vsupply_revabc?
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<josHua[m]1>
I willingly ride a singlespeed bicycle on long, climby days, and even I would not write 8051 asm if I did not have to.
<josHua[m]1>
C gives you... `uint16_t codeword = (254 << 4) - ((((mgmt_req.vsupply.value[chan] - 1650) >> 4) * 269) >> 4);`, which is something that modern humans are much better at reasoning about than the 8051 equivalent
<whitequark>
SDCC does not do any non-local optimizations
<whitequark>
tpw_rules: have you written 8051 assembly?
<tpw_rules>
i know it's awful
<whitequark>
have you seen what the expression above expands to?
<whitequark>
or, even better: can you write the assembly for it?
<ldcd>
wondering if it makes sense to break out the +/-15V to power external opamps
<ldcd>
but one would probably usually want a seperate linear split rail generator if they need to make their own AFE for the NAFE
<ldcd>
given i think generally the iobank supplies are not really intended as power supplies and having +/-15V on the headers could lead to accidental damage of DUTs if someone plugs stuff in wrong
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<ln[m]>
i could put it on an extra header, i already put the common of the NAFE on two extra pins to the side. but it would need to be characterized if it changes NAFE performance significantly if there’s more load on the bias supply
<ldcd>
it already looks pretty tight just looking at the layout
<ldcd>
not sure it would make sense
<ldcd>
and if you're building an external front end there's a decent chance you want a linear supply anyways for that bit
<ln[m]>
just need to up it to 10L and then i’ll have all the space :3
<ldcd>
lol
<whitequark>
ldcd: oh the iobank supplies are used as programmable power supplies a lot
<whitequark>
the flexibility they have is quite intentional to that end
<ldcd>
huh
<ldcd>
for some reason in my head i had it that they were not intended that way
<duskwuff0[m]>
re. power_params: I'm sure there are Reasons but are we certain there needs to be a single FX2 firmware which runs on all revisions, rather than specialized ones for each
<whitequark>
duskwuff0[m]: people keep telling me that
<ldcd>
i will definitely start using them that way lol
<whitequark>
but do you want to build something like 5 firmwares, of which 1-2 for obsolete revisions we support out of goodwill alone?
<whitequark>
it's not just about avoiding #ifdef hell (though it's definitely that); it's also about genuine commonality between revisions (we haven't had a complete clean break between any two revs)
<whitequark>
assuming by "specialized" you do in fact mean ifdef hell
<whitequark>
if you mean copying the firmware and modifying in-place then that would mean end of support of anything before C3 right away
<whitequark>
because there's no way i'm going to keep track of whether every single protocol change goes into revA
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<whitequark>
ldcd: i use them as power supplies allllll the time
<whitequark>
starting with C3 they have some quite nice safety features
<whitequark>
like voltage and current alerts which disable the power supply using hard logic (a diode)
<ldcd>
oh nice
<ldcd>
i did not know that
<whitequark>
it's not very well exposed
<whitequark>
the voltage brackets are configurable via the CLI
<whitequark>
the current limit is currently, uh
<duskwuff0[m]>
ifdefs or something equivalent but yes. I totally understand where you're coming from - at the same time you're kind of just replacing ifdef hell with, uh, if(version) hell
<whitequark>
not implemented in the firmware
<whitequark>
but it's something i plan to do before revD is shipped
<whitequark>
and it'll work on revC3 too
<whitequark>
duskwuff0[m]: exactly! so it's not worse and it saves me from building more than one hex file
<duskwuff0[m]>
also: is it intentional that valert/vsense are sometimes swapped in those structure definitions?
<whitequark>
no i fucked up
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<zyp[m]>
ifdef hell is for when the required variant can be built on demand; when firmware is prebuilt you're better off if you don't need to manage variants
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<whitequark>
basically yes
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<zyp[m]>
we have some projects at work that consists of multiple different boards with entirely different functions that still runs a common firmware
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<WilfriedWonkaKla>
I remember a hardware device from a previous workplace where they had one UI module and several different device slot modules, and they all ran the same firmware
<WilfriedWonkaKla>
but there were not many different hardware revisions, luckily
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<whitequark>
things that are shockingly inefficient on a 8051
<whitequark>
1<<i
<whitequark>
that expands into 24 instructions
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<tpw_rules>
what was wrong with a loop
<whitequark>
hm?
<tpw_rules>
is 8051 so bad that you cannot do that with a like four instruction loop?
<tpw_rules>
re the earlier discussion the project i'm on builds like 500 firmwares so 5 is no big deal. that might be easier than scrimping for bytes. but i'm not sure if i'm contributing something useful, i did not completely follow the earlier discussion
<whitequark[cis]>
this would not even make the firmware significantly smaller
<whitequark[cis]>
just makes it a pain in the ass to deal with
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<whitequark>
this compiler is so dumb
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