whitequark[cis] changed the topic of #glasgow to: https://glasgow-embedded.org · digital interface explorer · https://www.crowdsupply.com/1bitsquared/glasgow · code https://github.com/GlasgowEmbedded/glasgow · logs https://libera.catirclogs.org/glasgow · matrix #glasgow-interface-explorer:matrix.org · discord https://1bitsquared.com/pages/chat
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<whitequark> ok so i'm on the verge of declaring end of support for <=revC2
<whitequark> they have an ADC with a silicon bug which locks up the I2C bus if you read a certain bit pattern out of the ADC
<whitequark> yes, it's as insane as it sounds
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<tpw_rules> that sounds like a fun errata sheet
<whitequark> it seems like there's some sort of issue that arises only when the internal oscillator is enabled
<whitequark> the workaround is to never use the ALERT function basically
<whitequark> which... ok, fine, i'll add a notification about that
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<_whitenotifier-e> [glasgow] whitequark opened pull request #1181: [WIP] Reimplement firmware and management protocol; add revD support - https://github.com/GlasgowEmbedded/glasgow/pull/1181
<_whitenotifier-e> [glasgow] whitequark synchronize pull request #1181: [WIP] Reimplement firmware and management protocol; add revD support - https://github.com/GlasgowEmbedded/glasgow/pull/1181
<_whitenotifier-e> [glasgow] whitequark synchronize pull request #1181: [WIP] Reimplement firmware and management protocol; add revD support - https://github.com/GlasgowEmbedded/glasgow/pull/1181
<_whitenotifier-e> [glasgow] whitequark synchronize pull request #1181: [WIP] Reimplement firmware and management protocol; add revD support - https://github.com/GlasgowEmbedded/glasgow/pull/1181
<_whitenotifier-e> [glasgow] whitequark synchronize pull request #1181: [WIP] Reimplement firmware and management protocol; add revD support - https://github.com/GlasgowEmbedded/glasgow/pull/1181
<q3k[cis]> whitequark: can you unwedge the ADC with one of those i2c reset procedures (iirc pulse the clock until you see sda be released, then generate a stop?)
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<whitequark> q3k[cis]: for that one specific problem, yes
<whitequark> but i found a second problem, which is that under the same conditions (aggressively reading/writing a read/write register) the ADC sometimes just... wedges itself into an even weirder state where writes to registers don't take
<whitequark> or possibly reads, it's not possible to determine for sure
<q3k[cis]> how quaint
<whitequark> that is only fixed by power cycling
<q3k[cis]> what's the P/N?
<whitequark> adc081c021
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<whitequark> i already complained to someone on ti on mastodon and they promised to give an intern a task to reproduce this
<q3k[cis]> oh is that the chip you have been yelling about on...
<whitequark> *at ti
<q3k[cis]> yeah
<whitequark> yes
<q3k[cis]> what speed are you running i2c at?
<q3k[cis]> (i'm not trying to troubleshoot this for you, i'm just curious)
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<whitequark> tried both 100/400
<whitequark> 400 is the normal one
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<_whitenotifier-e> [glasgow] whitequark synchronize pull request #1181: [WIP] Reimplement firmware and management protocol; add revD support - https://github.com/GlasgowEmbedded/glasgow/pull/1181
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<whitequark[cis]> how it's going
<whitequark[cis]> to be clear, this is a completely different TI chip (revD DAC rather than the revABC01 ADC)
<whitequark[cis]> writes seem to work, reads lose about half to three quarters of the bits of every byte. no i can't explain it better
<whitequark[cis]> at least here a good number of workarounds is available. I just can't bring myself to trust a device that behaves like that
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<ldcd> DAC43204?
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<whitequark[cis]> yes
<ldcd> i really wish the nanoDAC series was less expensive
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