05:32 <Mathias[m]> <whitequark[cis]> probably also whatever arm's version of SEV is called

05:32 <Mathias[m]> The larger name is Arm CCA (Confidential Computing Architecture) which includes firmware interfaces, built on the RME (Realm Management Extension) feature of the architecture (Armv9.2-A if memory serves).

05:47 <whitequark[cis]> thank you

08:53 <thejpster[m]> <thejpster[m]> is this an LLD bug?

08:53 <thejpster[m]> I think this is an ld bug.

16:59 <ruabmbua[m]> has anyone ever tried to get embassy-executor, riscv, riscv-rt working on rv32e architecture?... (full message at <https://catircservices.org/_irc/v1/media/download/Af9jyBHtnFs0XGhJtHIuQOf3LYK9WANPtERi0mKIct108GGGK1NAe4sjlVVLZuoQYogImZpxbIMQpPRfBCONbs-_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9PbVdsd2hLUUdXRFdDVkhmY0JRZ2VvTlg>)

17:27 <i509vcb[m]> The executor shouldn't necessarily care about the reduced register file.

17:27 <i509vcb[m]> The compiler will just register allocate differently

17:31 <ruabmbua[m]> yeah, only trap handler assembly should matter, and it seems correct.

17:32 <ruabmbua[m]> What I also noticed is that the toolchain does not generate the correct elf metadata attributes.

17:32 <ruabmbua[m]> it leaves out the extensions for whatever reason, and gdb stupidly decides to not disassemble instructions that are not whitelisted in the elf file...

17:35 <ruabmbua[m]> currently trying to force it via... (full message at <https://catircservices.org/_irc/v1/media/download/AYMDNQ4GycbtcqLw-s1hYavnRZfNnnaTqDwb6y0V33nFd_qyBeTxEU_nTh90qZKC65JK09RE3G6Pl24WZI-jzbi_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9sSHBjQmJVS2l4am1hU1FkZmNYWHp5V1k>)

17:48 <ruabmbua[m]> idk what I did, suddenly the program runs

17:48 <ruabmbua[m]> very fishy :D

17:48 <ruabmbua[m]> switched between gnu linker and back, now it works.

18:06 <i509vcb[m]> Bad target json?

18:15 <JamesMunns[m]> or maybe check if riscv-rt asm is correct

18:15 <JamesMunns[m]> There was an issue recently that global asm I think wasn't handling target features right

18:17 <ruabmbua[m]> idk why but I checked now what I changed. Nothing. it suddenly started to work

18:17 <ruabmbua[m]> maybe incremental compilation / target file changes ?

18:17 <ruabmbua[m]> cargo clean could have helped..

18:18 <JamesMunns[m]> https://github.com/llvm/llvm-project/issues/61991#issuecomment-4877549106 was what I was thinking of

18:18 <thejpster[m]> building with --release breaks some inline asm

18:18 <thejpster[m]> or not --release - I forget. It was codegen-units related.

18:19 <JamesMunns[m]> https://github.com/rust-lang/rust/issues/127269 was your issue I think

22:18 <ruabmbua[m]> embassy running on my custom designed rv32ea +zicsr +zifenci core & soc in RTL simulation :-)

22:21 <ruabmbua[m]> The simpler in-order core is usable in simulation, this one not so much (13 clocks / host second ) :P

22:23 <ruabmbua[m]> I`ll have to test it with 2 cores next