03:06 <az1[m]> But those are all dependencies you'd add at the start of a project, right? In that context a template might be more useful.

05:39 <mkj[m]> I wonder if battery packs would be useful to tie together matching crate versions. like how in embassy you have to make sure you've got compatible versions of all the crates, similarly for some the rustcrypto crate ecosystem

09:19 <thejpster[m]> one challenge here is that many MCU families have multiple choices of HALs (rp-rs vs embassy-rp, stm32-rs vs embassy-stm32, etc).

09:19 <thejpster[m]> The Rust Embedded Working Group, as a rule, has never picked a favourite. It just explains what the options are.

10:00 <diondokter[m]> As promised, sequential-storage v8.0.0 is out now!... (full message at <https://catircservices.org/_irc/v1/media/download/AR78PCGKGAb6wwBA2Tgm-dlP-mMYiVhzpjK438VAvqLfzdVNq4H14-IjDbOraa7rn9y_NF9UdYsBIYDRa_hRctK_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9jZUxhcG9LY2xjd1BQRkhjY1ltYkFQd28>)

10:18 <dcz[m]1> is it a data race if I write a memory area over JTAG? it is, right?

10:20 <Darius> as in race with code that is executing?

10:20 <Darius> not if you halt the CPU(s) :D

10:21 <dcz[m]1> in the sense of "it's always UB to have a data race in Rust" :P

10:22 <dcz[m]1> well I can use Atomic types in the beginning

10:22 <dcz[m]1> the other question would be: how do I designate a well-known address to exchange data via JTAG?

10:23 <dcz[m]1> or do I analyze the binary symbols every time before I write data?

10:24 <dcz[m]1> there's #[link_section = ".foo"] but I don't know how much control I have over placement at a concrete address within the section

10:39 <thejpster[m]> this sounds like defmt-rtt, or any kind of RTT in fact?

10:40 <thejpster[m]> the compiler can put things in sections, and the linker chooses where to put the sections. If you want the section in a specific place you have to tell the linker to do that. Or you can let the linker place it, and you can ask the linker where it put it (on the target side) or look it up in the symbol table (on the host side)

10:41 <Darius> dcz[m]1: you should start with the problem you are trying to solve

10:42 <dcz[m]1> Darius: synchronize clock. Straight way from there: link to a computer via JTAG as the simplest, already present interface (ESP32). I need to declare a fixed address.

10:44 <Darius> easy enough to do that in a linker file

10:48 <dcz[m]1> weird, defmt-rtt has , link_section = ".uninit.defmt-rtt.BUFFER" but there's no linker file declaring that in the repo

10:49 <Darius> hm

10:50 <Darius> perhaps it expects you to pick an address/size

10:51 <az1[m]> https://github.com/knurling-rs/defmt/blob/main/defmt/defmt.x.in

10:51 <dcz[m]1> except it's not documented that you should pick it

10:52 <dcz[m]1> that linker file doesn't seem to have any "rtt" mention

10:56 <az1[m]> Right, the RTT buffer doesn't necessarily need a fixed location. You can either get the address from the symbol or IIRC scan the memory for the signature.

10:57 <az1[m]> With Cortex-M, the linker script from the cortex-m crate places the .uninit stuff appropriately.

10:57 <dcz[m]1> thanks. Gonna have to implement it and see what comes out. Also, probe-rs might have the code

10:59 <az1[m]> Yep, probe-rs will generally DTRT without having to manually place the buffer.

11:01 <dcz[m]1> I guess this will do: https://docs.rs/probe-rs-rtt/latest/probe_rs_rtt/

11:01 <dcz[m]1> since I don't want to implement JTAG myself...

11:02 <az1[m]> If you need bidirectional comms you should also look at rtt-target

11:02 <dcz[m]1> yup, already on my list :)

11:02 <dcz[m]1> that actually solves another problem of mine (moving data out of the chip), so double thanks

11:59 <JamesMunns[m]> <dcz[m]1> is it a data race if I write a memory area over JTAG? it is, right?... (full message at <https://catircservices.org/_irc/v1/media/download/AVpUxQ6k5CQrf2T1MogFSsKrODqtd4GNJQr6s4B38nMlx8VpF4SNaiq2e53ciur7ay3oboA5HTue6K6yakO31ay_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9qVkRVTGpXeGVqTm11SG9NdHJhSHlyUXo>)

12:00 <JamesMunns[m]> <dcz[m]1> is it a data race if I write a memory area over JTAG? it is, right?

12:00 <JamesMunns[m]> I mention this, because Hubris (and our debugger, Humility), do this a _lot_, and there has been a lot of hammering to make sure _how_ we do it is sound and doesn't lead to miscompilations.

12:05 <JamesMunns[m]> Debuggers can't necessarily directly participate in things like atomic CAS operations, it might be necessary to halt the core if you need to do a read/modify/write loop for "check if the lock is taken, and if not, take the lock", or you can use "asynchronous" coordination like RTT does, where the core and debugger aren't trying to write the same address at the same time (one moves the read pointer, one moves the write pointer)

16:49 <HarshVerma[m]> Hi folks, I'm Harsh, I was looking for some rust related repositories where i can contribute and I came across heapless, am I in the correct channel?

17:02 <thejpster[m]> yes the heapless maintainers will be here (but they'll also be in #rust-embedded-wg:matrix.org )