11:28 <RobinMueller[m]> does anyone who is more knowledgeable in RISC-V have an idea why this processor I have flashed is stuck on the third instruction?... (full message at <https://catircservices.org/_irc/v1/media/download/AWl4O8SPjf3Z41JOG1uL78hV7k8Sw_ETjgiq8GyKXy4s5WroiepUKFV53Zbl8E40cFU_9n-HwS8Z6-yWD6wE-T6_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9KdGduTU9JdGx0Rkh0dXVxUmRmcXd6a28>)

11:37 <thejpster[m]> Is your CPU pipelined? Is it falling to read something up ahead?

11:38 <RobinMueller[m]> ah, you mean it actually possibly fails on the next instruction?

11:40 <RobinMueller[m]> > The NOEL-V integer unit uses a dual-issue instruction pipeline with seven stages

11:46 <RobinMueller[m]> i have instantiated the single issue pipeline variant of the core though

11:51 <RobinMueller[m]> i think i will just ask in their support forum. i built the core with the supplied default config and i can probe all the AHB masters and i can also probe the core registers using their monitoring tool. but executing instructions seems to be problematic. i can only make code execution work on a 3 year old pre-built design 😅

12:15 <RobinMueller[m]> * code execution properly work on

17:07 <AstraKernel[m]> I am not sure i can share this. if it is not allowed, please let me know. There is new Embedded Rust meetup. Orhun Parmaksız doing the inaugural speech currently. if anyone interested, can join https://t.co/xJbSsbkY1C

17:48 <thejpster[m]> I minimised my qemu-system-arm issue with the mps3-an524 machine.... (full message at <https://catircservices.org/_irc/v1/media/download/AQZPUC43CtuYct1J8naoTAKXS_jLr2oV7rAU_0kU3d8uPWkHd0vn4QLQq5CQb2_oS8TPGDeWUB6qevlpRf9YRJe_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy93UVZ4cEFGcmJjcUpnS0lDZUFSSExZZHA>)