<whitequark[cis]>
we should have a write_vcd() variant that only writes the files if the tests fail
<Wanda[cis]>
I think TDO is supposed to change on the falling edge?
<whitequark[cis]>
technically yes
<whitequark[cis]>
do we care?
<whitequark[cis]>
EXTEST is also mandatory and i'm definitely not mandating that
<Wanda[cis]>
it sounds like the kind of thing that'd end up causing weird problems at a completely unexpected moment
<Wanda[cis]>
so hm. this is not exactly the "conventional" way of implementing TAPs
<Wanda[cis]>
you have one shift register for everything instead of multiple shift registers, and then you have the separate "update" registers which are per-instruction
<Wanda[cis]>
I'm not sure if the single SR is actually a win; it results in many muxes (from all the capture inputs) instead of a single mux and more FFs spent on SRs
<Wanda[cis]>
the latter option sounds like it would have better locality (it certainly would if there were actual bscan registers involved)
<Wanda[cis]>
I also don't see a way to implement an actual readable/writable register with the interface as it stands (there is no write strobe)
<whitequark[cis]>
you just use the controller state
<whitequark[cis]>
i've considered adding strobes but people love to implement weird shit like "this register only matters in RTI" so i am going to completely ignore the whole "strobe" business. go match TAP state for anything
<whitequark[cis]>
* i've considered adding strobes but people love to implement weird shit like "this register only does anything in RTI" so i am going to completely ignore the whole "strobe" business. go match TAP state for anything
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<whitequark[cis]>
the single SR is for usability reasons rather than optimization, you usually want the state retained past Update-DR
<whitequark[cis]>
and having it shift under you in Shift-DR may have unintended consequences
<whitequark[cis]>
like right now i'm looking at a doc for an ARM core where in Shift-DR the patterns you shift in appear on the actual memory bus. hope none of that has any side effects
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<whitequark[cis]>
hm, I guess we could implement a more compliant TAP by usng DDR buffers
<whitequark[cis]>
s/usng/using/
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<zyp[m]>
I like the mux approach, it means you can have an IR value ignore the whole shift register business and mux in a synchronous serial interface instead: https://paste.jvnv.net/view/9Vefv
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<Chips4MakersakaS>
<whitequark[cis]> "do we care?" <- I do think you need to care as likely JTAG probes will sample TDO on rising edge so if you change TDO on rising edge the chance of having metastability in the probe is high.
<zyp[m]>
can't you just have a second domain on the falling edge that clocks a buffer on TDO?
<zyp[m]>
AIUI that's what the ECP5's JTAGG primitive does
<zyp[m]>
DDR buffers sounds like too much latency
<whitequark[cis]>
<Chips4MakersakaS> "I do think you need to care as..." <- you sample at the same time as changing TCK, which is fine
<whitequark[cis]>
just need zero hold time requirement
<whitequark[cis]>
<zyp[m]> "can't you just have a second..." <- it starts to become a pain at that point, although i guess now that we have local domains and a fully functional simulator, not so much
<Chips4MakersakaS>
<whitequark[cis]> "just need zero hold time..." <- I don't think you can assume that existing JTAG probes are compliant with zero hold time requirements.
<whitequark[cis]>
i actually wonder how many devices implement this correctly now
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<_whitenotifier-2>
[amaranth-lang/amaranth-lang.github.io] whitequark ccaa874 - Deploying to main from @ amaranth-lang/rfcs@98c79d3f1b42eb19546af14dcf9d837c02f97547 🚀
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<_whitenotifier-2>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] b249259 - Deploying to main from @ amaranth-lang/amaranth@fd41201e20592f412b15fd33fd29a9eb36899c69 🚀