jackdaniel changed the topic of #commonlisp to: Common Lisp, the #1=(programmable . #1#) programming language | Wiki: <https://www.cliki.net> | IRC Logs: <https://irclog.tymoon.eu/libera/%23commonlisp> | Cookbook: <https://lispcookbook.github.io/cl-cookbook> | Pastebin: <https://plaster.tymoon.eu/>
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<jasom> gilberth: amd64 is not as register starved as x86, but neither is it as overfed on registers as Power. In testing I've done (by reserving registers on a Power machine), somewhere around 16 truly general registers (i.e. not including SP, PC, FP, LR) is where diminishing returns of having more registers start to kick in. POWER and MIPS easily have this, even with two stacks, but aarch32 and amd64 do not.
<jasom> gilberth: There is a strong argument to be made that precise garbage collection is worth the performance hit that a dual-stack amd64 implementation would have, but I predict that there would definitely be a performance hit on real world code.
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<beach> gilberth: I see, thank you. I may have questions later.
<beach> gilberth: If the whole heap gets relocated, then every pointer in it must be modified, no?
<beach> gilberth: I can see how a jump table to subroutines would solve the relocation of code, but I don't see how it will solve the relocation of data. When you take the CAR of a CONS cell, the result had better be a valid pointer into the heap, so if the heap is relocated, that pointer has to be updated, no?
<beach> gilberth: Unless of course every heap access is indirect through some base pointer.
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<aeth> jasom: looking up the number of registers, apparently Intel doubled the number of registers from 16 to 32 in a fairly recent extension (2023ish?)... https://en.wikipedia.org/wiki/X86#APX_(Advanced_Performance_Extensions)
<aeth> So I guess compiles can assume it's present in 15+ years.
<aeth> *compilers
<aeth> Too bad they didn't do this in Haswell in 2013 because then we'd have this on nearly every Intel and AMD CPU by now.
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<equwal> l
<ixelp> GitHub - equwal/posix-pipes: portable pipes
<equwal> do we need this
<beach> Looks useful for what some people do.
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<equwal> ok thanks
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<jackdaniel> equwal: you may be interested in systems like external-program and, if you must, uiop that aim at providing full external program api compatibility layer
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<drmeister> Hey everyone. Is anyone using ocicl? How does it contrast to quicklisp?
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<mesaoptimizer> I still use quicklisp because I am lazy, I hope to eventually move to vend
<mesaoptimizer> ocicl looks quite complex and not very lispy to me, somehow
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<xcombelle> hello
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<gilberth> beach: The jump table is in address space below 4GB for the sole reason that an instruction like "jmpq *1234" is used and that instruction only takes a 32-bit address.
<gilberth> beach: For the heap. Even with ASLR it is still possible to mmap(2) pages at will provided that the pages aren't taken yet. ASLR only applies to the operating system's loader and dynamic linker putting your segments from the binary file at random addresses.
<gilberth> beach: So even with ASLR you can map the heap where you want it. The routine in CCL to relocate the heap image if needed is there for robustness in case that the very address range we picked would not be available. And yes, it goes over the whole heap image and relocates pointers. GC must be able to that anyway.
<gilberth> jasom: With AMD64 we would have enough registers to afford a second stack pointer. And modern CPUs don't care whether you use the PUSH instruction or the equivalent sequence of instructions using another register as the stack pointer. Note that CCL already partitions registers into pointer registers and immediate value registers. And in general the compiler cannot make good use of having plenty of registers available.
<gilberth> jasom: Which imho is a bit overrated. It's only important for tight loops with no function calls at all.
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<gilberth> jasom: Further. When coming from i386 and going to AMD64 you get eight extra registers. This switching %rsp back and forth is annoying and is a nightmare with signal handlers. It confuses both the kernel and me. And it confuses Rosetta. So I say that crafting the AMD64 from the PPC port with having two stack pointers would have been saner.
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<gilberth> jasom, beach: And wrt to that jump table I plan to have a register set aside for NIL. It would not only point to NIL but also have that jump table nearby. It'll actually be a kind of pointer to a bunch of global data.
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<beach> Hello xcombelle.
<beach> gilberth: I see. Thanks.
<beach> Oh, a register for NIL is a good idea.
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<xcombelle> hello beach
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<beach> xcombelle: Are you still learning more about Common Lisp?
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<mesaoptimizer> ::notify fosskers you might want to get vend on https://awesome-cl.com/ eventually
<Colleen> mesaoptimizer: Got it. I'll let fosskers know as soon as possible.
<ixelp> awesome-cl
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<xcombelle> beach: I'm currently doing advent of code 2024 in python
<beach> Oh!
<xcombelle> I'm too much fluent in python to make the switch
<beach> I am sorry to hear that.
<xcombelle> I have to find easier tas than aoc
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<beach> For Common Lisp or for Python?
<beach> For Common Lisp, you can look at the exercises in one of the Common Lisp books. Perhaps ANSI Common Lisp, though I haven't checked that it has exercises.
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<yitzi> xcombelle: There is also https://exercism.org/ They used to have a CL course.
<ixelp> Exercism
<mesaoptimizer> xcombelle: https://docs.codewars.com/languages/commonlisp/ might be useful to you
<ixelp> CommonLisp | The Codewars Docs
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<mesaoptimizer> there's also the Euler Project, but I think you cannot really avoid studying at least half a dozen chapters from one of the introductory CL textbooks
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<xcombelle> I love programming languages my main misses are lisp, ocaml and haskell
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<jasom> gilberth: Very hot codepaths on SBCL benefit heavily from inlining (not just due to function-call overhead, but also elision of type checks) and that can stress the register allocator.
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<gilberth> jasom: It doesn't matter for what I'm interested in. And it doesn't matter too much for CCL. So the extra eight registers are plenty, which is what I said. Besides the "B" in SBCL should stand for "batch". I don't like that I cannot reliably redefine a single function but must compile and load the whole source file again when I make changes.
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<attila_lendvai> phantomics_, hi, i'm pondering... does it have value to be able to switch the execution mode at runtime? or shall i just bite the bullet and emit the instructions in various isolated packages, e.g. 32/base/functional, 64/sse/macro, ... but i think this quickly blows up...
<attila_lendvai> the question that brought me here is that some instructions (e.g. pextrb) needs to dispatch on the execution-mode when decoding the register name. now, in my current infrastructure that happens at macroexpand-time, which is too early. moving that code to runtime would be quite a reorg...
<attila_lendvai> if it ever gets to that, then i may consider writing a simple partial evaluator and resolve this whole issue by always building a complete form for an instruction, and then based on the bound variables let the PE simplify the form that will then go into the insrtuction-emitter, be it a function or a macro.
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<attila_lendvai> while we are at it, does a functional interface have value? i.e. does the implementation of e.g. a JIT compiler have asm instructions where the operand is not a literal register name, but comes as a runtime variable?
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<attila_lendvai> i believe it does have value, but i don't really know from experience
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<phantomics_> attila_lendvai, in my JIT system for April it creates internal variables, beyond that I'm not quite sure of your meaning there. Runtime execution mode switching is a property of x86 so my goal would be to facilitate it if desired
<attila_lendvai> phantomics_, some instructions must emit different machine code depending on the targeted execution mode
<attila_lendvai> ...and some operands are only allowed in 64 bit mode. but then there are tricky ones like pextrb where the MC depends both on the register class of the operand, and the current execution mode. (it's the GR32orGR64 type in the TableGen json)
<attila_lendvai> and what i meat is that in my initial experiment i generate macros as instruction emitters, and i think i'll need to turn them into functions for multiple reasons. then this whole question becomes moot, because macroexpand-time disappears.
<attila_lendvai> then (speed 3) and inlining can be used to simplify away from the code body when the register name is known at the call site
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<phantomics_> I'm familiar, the width byte specification works differently depending on your mode. It could definitely cause problems if you emit instructions in the wrong mode
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