_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<polprog> hi
<polprog> im trying to route a signal to an io pin, but vivado keeps changing the assignment
<polprog> i have this on my _io list: ("debugA", 0, Pins("T11"), IOStandard("LVCMOS33")),
<polprog> but when i inspect the project in vivado, i can see that debugA is the only pin which is not fixed, and it changes from T11 to T12
<polprog> is there something more i need to do in LiteX so that the generated xdc will have the pins fixed?
<polprog> never mind - looks like digilent has a mess in their schematics and T11 is ground
<polprog> x_x
<Flea86> polprog: Surely vivado would've thrown an error when you defined the io pin as T11?
<Flea86> or attempted to do so
<polprog> Flea86: when i run the build from LiteX it fails to generate the bitstream, of course, but when i sourced the .tcl in vivado gui it just moved the pin
<Flea86> I see
<polprog> [Common 17-69] Command failed: 'T11' is not a valid site or package pin name.
<Flea86> I don't use vivado at all
<polprog> there it is
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<Flea86> Correct, that is the error note
<polprog> for some reason Digilent schematics are completely wrong
<Flea86> :/
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