trabucayre changed the topic of #openFPGALoader to: Universal utility for programming FPGA / Github: https://github.com/trabucayre/openFPGALoader/ Logs: https://libera.irclog.whitequark.org/openFPGALoader
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<ysionneau> so, I now understand one of the big reason my SPI programming of ECP5 did not work : CS handling
<ysionneau> CS actually *needs* to be unasserted after each command so that the command completes
<ysionneau> I was keeping CS asserted all along
<ysionneau> so now I can correctly read "status register" and Idcode and send several commands that all seem to work
<ysionneau> nevertheless it's still not good at the end: DONE stays at 0 and end status register is 0x1000020e
<ysionneau> what's not clear is what to do with CS while clocking in the bitstream
<ysionneau> since ... the bistream is somehow made of a sequence of commands...
<ysionneau> do I just keep CS asserted and send all the bitstream ? (it does not seem to work) of do I need to interpret all bitstream commands to assert/unassert the CS at each bitstream's command?
<trabucayre> some command must be exactly 8bits