09:36 <karlp> 5was still good to see a long standing big ticket get through in the end :)

12:01 <Haohmaru> huh, _now_ i notice that besides SWCLK SWDIO SWO, my chip also has 4 TRACE signals

12:03 <Haohmaru> oh and a TRACE CLK

13:21 <karlp> that's etm.

13:26 <Haohmaru> yeah, i hadn't noticed the signals before, i guess i had the impression that the ETM thing happens via the SWO thing, since the SWO is "fancier" (not present on dumber chips)

13:26 <karlp> swo is on everything except shit tier M0.

13:26 <karlp> etm is the fancy big boy trace.

13:27 <Haohmaru> so two levels of fancyness

13:27 <Haohmaru> poor cortex-M0(+), no one seems to like them around here

13:30 <Haohmaru> i dislike them a bit myself now that i found out that their multiplier may be slow (not on my chips, but it means i have to check this when i look at other chips)

13:30 <Haohmaru> more than 1 clock cycle for x*y is not fun

17:56 <zapb_> karlp, actually that's TPIU with more than one signal. you can send ITM over 4-bit parallel if you like :D

22:13 <karlp> sure, but I'd argue that's an unhelpful hair to split