<Wanda[cis]>
current status: writing the new data structures for timing databases (to be used for siliconblue now, extended for other FPGAs later)
<Wanda[cis]>
I'm also migrating the existing CPLD timing databases to these structures while I'm at it, and my meowing gods those are so crude
<Wanda[cis]>
how on earth am I supposed to trust a delay value that's a single number and not a range
<Wanda[cis]>
I guessss at least CPLDs are simple enough devices that you can just do timing analysis in a "don't worry about it kitten" manner?
<Wanda[cis]>
it's fiiiiiine, I'll just upgrade these delays to [val, val] delay ranges, assume missing removal and hold times are zero, and generally not think about it too much
mei[m] has joined #prjcombine
<mei[m]>
yeah, you're a kitten, clearly you shouldn't worry about it