<Wanda[cis]>
what the fuck is wrong with this derating formula
<Wanda[cis]>
isn't logic supposed to get slower when temperature rises or something
<Wanda[cis]>
ah, it's only ice40LP that goes faster with temperature. ice40HX goes slower. okay carry on then.
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<whitequark[cis]>
amazing
<Wanda[cis]>
alright, recovered the whole thing
<Wanda[cis]>
so there's a base delay for everything
<Wanda[cis]>
which is multiplied by process_factor * (1 / (av² + bv + c)) * (dt + e), with a, b, c, d, e being family-specific constants, and the process_factor being one of three family-specific constants depending on min/typ/max corner selection
<Wanda[cis]>
iCE65L (but not iCE65T nor iCE65P) also gets slightly fancier with separate d, e coefficients for each of three corners for some reason
<Wanda[cis]>
which means I get to remove min/max ranges from the timing database and only store the single base delay everywhere
<whitequark[cis]>
nice
<Wanda[cis]>
also they just... used the same number for the min/typ/max process factors for iCE40HX? so pretty much the entire min..max variation comes from voltage tolerance (and a bit of temperature variance for the rest)?
<Wanda[cis]>
so that's why the HX timing spreads are so tight
<Wanda[cis]>
oh. and the base delays are actually identical between iCE40LP and iCE40HX.
<Wanda[cis]>
so actually... how are iCE40LP and iCE40HX made in the first place?
<Wanda[cis]>
like, it's clearly the exact same netlist, just... with a different process?
<Wanda[cis]>
do you like... fudge some process parameters, reuse the same mask, and magically obtain something faster but with higher power usage? or is that more involved?
<mupuf>
they could also have made a new mask with the same hardware design
<mupuf>
just ported the design to a different node... or the foundry's PDK abstracted the difference away, like TSMC's 7 and 6nm
<Wanda[cis]>
the node is TSMC 40nm in both cases
<mupuf>
TSMC does offer different variants of the process, maybe that's all there is to it?
<galibert[m]>
FWIW the hundreds of skus for cyclone V end up being 7 different dies, no more
<whitequark[cis]>
i suspect the difference between LP and HX is something like a difference in the gate oxide thickness
<Wanda[cis]>
oh that would make sense
<vup>
you also have different flavors of threshold voltage in one process node (via changing the channel doping), so maybe they just swapped high threshold voltage cells with low threshold cells?
<_whitenotifier-2>
[prjunnamed/prjcombine] wanda-phi 652e003 - Deploying to gh-pages from @ prjunnamed/prjcombine@8f07219b6f14a481da802562bcf2916ea47ca95d 🚀
<Wanda[cis]>
continuing the theme of "Wanda asks questions due to her complete lack of EE knowledge"
<Wanda[cis]>
say you're making an ASIC and doing timing analysis
<Wanda[cis]>
how do you figure out how time/voltage affects the timing?
<Wanda[cis]>
are there like ... formulas to calculate this shit from transistor geometry?
<galibert[m]>
Transistor geometry and material characteristics. It's kind of complicated, and they seem to have to measure a lot of stuff. The nice thing about standard cells is that it probably has already been measured and modeled
<galibert[m]>
quartus_sta does electric-level simulation, I reproduced it in mistral if you're curious
<vup>
If you want to do timing analysis for full custom designs, you usually use something like cadence liberate to extract timings of your full custom cell using some vendor provided spice transistor models. Wether something like voltage / temperature dependency there is just modeled by providing different transistor models for different corners or if can plug in temperature as a variable is pdk dependent to my understanding.
<vup>
for mosfets something like the bsim models are commonly used, and those include temperature dependencies