ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.catirclogs.org/yosys/ | Bridged to #yosys:matrix.org
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<Hammdist94> after `abc -lut`, how can I get the lut depth of a design?
<Hammdist94> encountered bigger problem; `abc -lut 2` produces designs with lut3s
<lofty[m]> I think the ABC output actually tells you the LUT depth of the design; I think it calls it `level`
<lofty[m]> Can you pastebin your Yosys log?
<lofty[m]> Hammdist94: ^
<Hammdist94> ah yes, lev=6 in my case, when I switch to abc9 (abc regular does not show this). I wasn't using abc9 because it seemed to perform worse but now it seems abc is cheating by using larger luts than allowed so I will try to stick with abc9 for now
<Hammdist94> is there anywhere that I could find an example of a techmap file for luts?
<Hammdist94> I think I got it to make LUT2 by copying and editing a file from ice40 default techlibs
<Hammdist94> however it still doesn't show the LUT constants in the tabular output (nor blif) but only in verilog output
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<lofty[m]> define "perform worse"
<lofty[m]> Most likely ABC9 has actually found a lower-delay solution for your design, and this solution has less timing slack to recover area.
<lofty[m]> (and a note on IRC etiquette: when replying to somebody make sure to mention their name, otherwise it takes three hours for them to respond)
<Hammdist94> that's certainly possible since plain abc does not show the lev value I cannot easily tell
<lofty[m]> what's the output format you want to use? you keep talking about "tabular format"(?)
<lofty[m]> (do you mean the output from stat?)
<Hammdist94> no, the output from yosys output_table command
<Hammdist94> it's easier to parse than verilog and doesn't contain aliased wire names but has no LUT constant information
<Hammdist94> oh, I found it can be added by editing the techmap definition of the lut: LUT2 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .C0(LUT[0]), .C1(LUT[1]), .C2(LUT[2]), .C3(LUT[3])); ... notice how the LUT table constants are fed as inputs which appear in output_table
<lofty[m]> There...is no output_table command in yosys
<lofty[m]> I guess you mean write_table? which is not really designed for that.
<lofty[m]> If you want something parseable, why not use the JSON output?
<Hammdist94> ah yes sorry it's called `write_table` analogously to `write_verilog`
<Hammdist94> maybe I will try the JSON sometime
<lofty[m]> That command has been basically untouched since 2017
<lofty[m]> it's true that parsing verilog is hard, which is why the JSON format is intended for "I want to process the output of Yosys" tasks.
<lofty[m]> what's your synthesis target, by the way? LUT2 chips are not very common.
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<Hammdist> lofty[m]: I was looking at dual LUT2 chips .. basically 74x153 .. until I realized the select lines are common to both of the "LUT2" in the package, making them not very useful for this purpose. now I'm thinking LUT3 with 74x151
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<lofty[m]> Hammdist: the thing is, using muxes as LUTs is kind of logic inefficient; you want to use them as muxes.
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