05:51 <_whitenotifier-4> [amaranth] joelpmichael opened issue #1610: Improving comparison handling of Python enum.Enum vs amaranth.lib.enum.Enum - https://github.com/amaranth-lang/amaranth/issues/1610

05:52 <_whitenotifier-4> [playground] ld-cd commented on pull request #9: Display waveforms for all instantiations of a given VCD ID - https://github.com/amaranth-lang/playground/pull/9#issuecomment-2995020652

06:32 <_whitenotifier-4> [playground] whitequark commented on pull request #9: Display waveforms for all instantiations of a given VCD ID - https://github.com/amaranth-lang/playground/pull/9#issuecomment-2995104010

06:32 <_whitenotifier-4> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±4] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/173a4af905a3...2029db89d293

06:32 <_whitenotifier-4> [amaranth-lang/amaranth-lang.github.io] whitequark 2029db8 - Deploying to main from @ amaranth-lang/playground@dc25433e0d8d0f2ce95126c95579e462b16271cb 🚀

15:13 <widlarizerEmilJT> Hi, I just checked that you're never emitting dffsr RTLIL cells from amaranth. That's good, keep not doing that. I'm pretty sure the documentation and verilog models are wrong about set/reset priority, as yosys seems to secretly reserve the right to do anything it wants when both are asserted, and its verilog frontends emit logic that ensures they're never both asserted

15:13 <widlarizerEmilJT> are there any other notable RTLIL producing projects I should go check?

16:52 <whitequark[cis]> no meeting today: there is nothing on the agenda

17:29 <whitequark[cis]> <widlarizerEmilJT> "are there any other notable..." <- not sure anyone except for amaranth is doing it

17:32 <_whitenotifier-4> [playground] ld-cd commented on pull request #9: Display waveforms for all instantiations of a given VCD ID - https://github.com/amaranth-lang/playground/pull/9#issuecomment-2997305980