<RobTaylor[m]>
random question just because there are smart experienced people here... if you've had experience doing PCB design for BGAs, what do you find are the the best pinout features that make life easier?
<whitequark[cis]>
ask azonenberg, he had a thread on this just a few days ago
<Stas[m]1>
I have not done BGA myself, but used his videos for PCB design
<Stas[m]1>
here he deals with a lot of BGA layout, as he is hooking up ddr2 to a fpga
<Stas[m]1>
There is a whole video series where he builds the board
<Stas[m]1>
There were interesting tips like, leaving vias open on the other side for probing
<zyp[m]>
I can't say I have a lot of experience with BGA layouts, but I've done some, and the nicest ones are the FPGAs since you're very free to pinswap signals to reduce the number of signal crossings you need in the layout
<zyp[m]>
for the non-FPGAs, it tends to vary how sanely they've grouped related signals so they can be routed together
<zyp[m]>
I've seen BGAs where memory interfaces are nicely grouped in a corner and I've seen BGAs where memory interface pins are all over the place
<zyp[m]>
if I were designing a BGA pinout, I'd also think about which «ring» each signal ends up in, since that puts constraints on which layers they'll be fanned out in, and it's often preferrable to have related signals fanned out in the same layer since they'll be going the same way and may then cross an unrelated group of signals fanned out in another layer
<_whitenotifier-4>
[amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1609-916791022cb9cf96a552756d0e00efe2a4b16aba - https://github.com/amaranth-lang/amaranth
<_whitenotifier-4>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 731c6cb - Deploying to main from @ amaranth-lang/amaranth@fa493208b6f1af998764d76b028aa1202f048555 🚀
<RobTaylor[m]>
<whitequark[cis]> "ask azonenberg, he had a..." <- Good idea :)
<RobTaylor[m]>
<Stas[m]1> "I have not done BGA myself..." <- thank you!
<_whitenotifier-4>
[amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1606-fa493208b6f1af998764d76b028aa1202f048555 - https://github.com/amaranth-lang/amaranth
<RobTaylor[m]>
<zyp[m]> "for the non-FPGAs, it tends to..." <- yep, i was thinking this. currently trying to figure out a basic algo for a nice way to group them..
<zyp[m]>
what size and pitch of BGA is this for?
<RobTaylor[m]>
<zyp[m]> "if I were designing a BGA pinout..." <- oh thats a really nice idea. I guess its a bit of a trade off of ring vs locality - I'm thinking of grouping by ring by quadrant as the core structure, then taking into account the other constraint satisfaction (pairs, lengths, em etc)
<_whitenotifier-4>
[amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 101818e - Deploying to main from @ amaranth-lang/amaranth@652dbef0399b73b48a4b56bd5e52e6e69bd2fc5a 🚀
<zyp[m]>
if you're targetting regular cheap PCB processes with e.g. a 0.8mm pitch BGA with four signal rings and power in the middle, you'd typically end up with outer two rings fanned out interleaved on the top layer and the inner two fanned out interleaved on the bottom layer, so it'd be convenient if the signal grouping were optimized for that
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<zyp[m]>
probably a bit different if you're targetting smaller pitch stuff like WLP on a HDI PCB
<zyp[m]>
I've never done anything that justifies the cost of HDI, so I don't have any experience with that :)
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<RobTaylor[m]>
<zyp[m]> "if you're targetting regular..." <- That makes sense
<RobTaylor[m]>
<zyp[m]> "I've never done anything that..." <- Yeah that’s probably not something I need to worry about near term , I hope!
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