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<Michiel[m]>
<sazzach[m]> Okay I've figured out the issue in your `Command-Wait-For-Ready` state. When the clock frequency isn't close to the bus frequency, the handshake for `ctrl.o_stream` finishes before the `ctrl.i_stream` handshake. This results in `should_tx` getting stuck at zero. The simulation clk freq is 1 MHz, and...
<Michiel[m]>
Thanks for having a look. I did not expect the `o_stream` to produce an output before the `i_stream` was consumed. With this change everything seems to work correctly! 😁
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