_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Guest17> Hi, I was wondering what is the recommended Jtag hardware that could be used to debug a litex risc-v cpu, and/or communicate via jtag-uart ?
<Guest17> I've tried with an Altera USB-Blaster, FTDI FT4232H MINI Module, HW-USBN-2B, Stm32 Blue Pill (flashed with dirtyjtag)... but haven't been able to get OpenOCD or Litex-term to work.
<Guest17> I'm using a Lattice ECP5 on a Colorlight v8 board.
<Guest17> The LiteX design instantiates a RiscV CPU and a jtag uart.. and I can program the bitstream using OpenFPGALoader and the DirtyJtag,
<Guest17> just can't connect to the CPU (OpenOCD v0.10 + dirtyjtag patch) nor see the LiteX banner that I imagine is transmitted via the jtag-uart at power on (via litex_term).
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