trabucayre changed the topic of #openFPGALoader to: Universal utility for programming FPGA / Github: https://github.com/trabucayre/openFPGALoader/ Logs: https://libera.irclog.whitequark.org/openFPGALoader
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<Guest94> openFPGALoader --cable digilent_hs3 -v --spi --unprotect-flash /path/to/.bit
<Guest94> empty
<Guest94> Jtag frequency : requested 6.00MHz    -> real 6.00MHz
<Guest94> ff ff ff ff read ffffffff
<Guest94> Detail:
<Guest94> Jedec ID          : ff
<Guest94> memory type       : ff
<Guest94> memory capacity   : ff
<Guest94> RDSR : 0xff
<Guest94> WIP  : 1
<Guest94> WEL  : 1
<Guest94> BP   : f
<Guest94> TB   : 1
<Guest94> SRWD : 1
<Guest94> Open file /home/abdulrahman/workspace/DET_TEST_25_MAR_NEW_APP_BOOTLOADER/_ide/bitstream/top_change_clk_wiz.bit DONE
<Guest94> Parse file DONE
<Guest94> RDSR : 0xfc
<Guest94> WIP  : 0
<trabucayre> don't add --spi
<trabucayre> to flash a xilinx you have to uses something like openFPGALoader --cable digilent_hs3 -v --fpga-part xc7a50t -f /home/abdulrahman/workspace/DET_TEST_25_MAR_NEW_APP_BOOTLOADER/_ide/bitstream/top_change_clk_wiz.bit
<Guest94> empty
<Guest94> write to flash
<Guest94> Jtag frequency : requested 6.00MHz    -> real 6.00MHz
<Guest94> found 1 devices
<Guest94> index 0:
<Guest94>     idcode 0x362c093
<Guest94>     manufacturer xilinx
<Guest94>     family artix a7 50t
<Guest94>     model  xc7a50t
<Guest94>     irlength 6
<Guest94> File type : bit
<Guest94> Open file DONE
<Guest94> Parse file DONE
<Guest94> bitstream header infos
<Guest94> date: 2025/03/13
<Guest94> design_name: top
<Guest94> hour: 14:09:37
<Guest94> part_name: 7a50tcsg325
<Guest94> ID Error        No ID error
<Guest94> DEC Error       0x0
<Guest94> XADC Over temp  0x0
<Guest94> STARTUP State   0x0
<Guest94> Reserved        0x0
<Guest94> BUS Width       x1
<Guest94> Reserved        0x0
<Guest94> jtag_chain_len: 1
<Guest94> SOJ version: 1.000000
<Guest94> 0 0 0 0 Read ID failed
<trabucayre> Ok seems to have an issue with spiOverJtag load
<trabucayre> and with --fpga-part xc7a50tcsg325 ?
<trabucayre> please adds each time openFPGALoader's output + you real cmd line
<Guest94> openFPGALoader --cable digilent_hs3 -v --fpga-part xc7a50tcsg325 -f /home/abdulrahman/workspace/DET_TEST_25_MAR_NEW_APP_BOOTLOADER/_ide/bitstream/top_change_clk_wiz.bit
<Guest94> empty
<Guest94> write to flash
<Guest94> Jtag frequency : requested 6.00MHz    -> real 6.00MHz
<Guest94> found 1 devices
<Guest94> index 0:
<Guest94>     idcode 0x362c093
<Guest94>     manufacturer xilinx
<Guest94>     family artix a7 50t
<Guest94>     model  xc7a50t
<Guest94>     irlength 6
<Guest94> File type : bit
<Guest94> Open file DONE
<Guest94> Parse file DONE
<Guest94> bitstream header infos
<Guest94> date: 2025/03/13
<Guest94> design_name: top
<Guest94> hour: 14:09:37
<Guest94> Release Done    0x0
<Guest94> Done            0x0
<Guest94> ID Error        No ID error
<Guest94> DEC Error       0x0
<Guest94> XADC Over temp  0x0
<Guest94> STARTUP State   0x0
<Guest94> Reserved        0x0
<Guest94> BUS Width       x1
<Guest94> Reserved        0x0
<Guest94> jtag_chain_len: 1
<Guest94> SOJ version: 1.000000
<Guest94> 0 0 0 0 Read ID failed
<trabucayre> I have no 50t to test in my side :-(
<Guest94> aha then no worry, is there any possible issue in mind? so I may investigate my self.
<trabucayre> I looks like the spiOverJtag bridge isn't correctly loaded / corrupted / no working
<trabucayre> But without a board with exactly the same device it's a bit hard to see if this is related to the bridge, issue with usb cable, OS, ...
<trabucayre> could you try without -f ?
<trabucayre> Just to see if you bitstream is correctly loaded in memory
<Guest94> I tried it, and it working fine
<Guest94> so mostly the issue with the spioverjtag
<trabucayre> weird
<trabucayre> I have tested the new spiOverJtag version with 35t/100t/75t/200t without issue
<trabucayre> and with different packages to validates the fact same bitstream works with different package
<trabucayre> could you try with --fpga-part xc7a_csg325_1v35 ?
<Guest94> openFPGALoader --cable digilent_hs3 -v --fpga-part xc7a50tcsg325_1v35 -f /home/abdulrahman/workspace/DET_TEST_25_MAR_NEW_APP_BOOTLOADER/_ide/bitstream/top_change_clk_wiz.bit
<Guest94> empty
<Guest94> write to flash
<Guest94> Jtag frequency : requested 6.00MHz    -> real 6.00MHz
<Guest94> found 1 devices
<Guest94> index 0:
<Guest94>     idcode 0x362c093
<Guest94>     manufacturer xilinx
<Guest94>     family artix a7 50t
<Guest94>     model  xc7a50t
<Guest94>     irlength 6
<Guest94> File type : bit
<Guest94> Open file DONE
<Guest94> Parse file DONE
<Guest94> bitstream header infos
<Guest94> date: 2025/03/13
<Guest94> design_name: top
<Guest94> hour: 14:09:37
<Guest94> Done            0x0
<Guest94> ID Error        No ID error
<Guest94> DEC Error       0x0
<Guest94> XADC Over temp  0x0
<Guest94> STARTUP State   0x0
<Guest94> Reserved        0x0
<Guest94> BUS Width       x1
<Guest94> Reserved        0x0
<Guest94> jtag_chain_len: 1
<Guest94> SOJ version: 1.000000
<Guest94> 0 0 0 0 Read ID failed
<Guest94> root@abdulrahman-X10DAi:/home/abdulrahman#
<Guest94> I'm using 4x SPI is it related by any mean?
<trabucayre> spiOverJtag uses 1x to be compatible with all devices/boards/configurations
<Guest94> what is the   --pins arg    pin config TDI:TDO:TCK:TMS or
<Guest94>                                 MOSI:MISO:SCK:CS[:HOLDN:WPN] used for?
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<trabucayre> it's when you uses a device in bitbang mode
<trabucayre> is your board custom or available?
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