11:05 <azonenberg> Are LUTRAMs particularly expensive or something from a transistor count / routing perspective?

11:06 <azonenberg> Curious why none of the efinix parts seem to have them

11:06 <azonenberg> (I just tried building one of my modules originally written for 7 series to Trion/Titanium and it's getting much worse synthesis results because some combinatorial-read register files got synthesized as DFFs since they don't map to BRAM)

11:07 <galibert[m]> iirc the mlabs on the cyclone are 30-50% bigger than the non-ram-able labs

12:27 <_whitenotifier-8> [prjunnamed/prjcombine] wanda-phi pushed 1 commit to main [+24/-0/±28] https://github.com/prjunnamed/prjcombine/compare/6d7fb6a66c5d...76fae809a351

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12:30 <Wanda[cis]> azonenberg: from routing perspective, they're pretty much identical to plain LUT (maybe a few more inputs, maybe not); however, LUTRAM does have significant complexity

12:31 <Wanda[cis]> you need memory cells which are writable by both the configuration logic and a second write path; you need address decoders; you need write pulse generators

12:32 <Wanda[cis]> and now your configuration memory becomes mutable, so if you have any kind of configuration ECC or readback CRC, you need to make a mechanism to mask off LUTRAM contents so LUTRAM changes don't register as configuration damage

12:35 <Wanda[cis]> further, nobody does only single-port LUTRAM; the usual thing to do is grab write address from one LUT within the logic block in particular and broadcast it over the block or something; you need to carefully design your logic block structure so that composes well with its other features

12:37 <Wanda[cis]> like, look at the Virtex 7 SLICE and its mux paths; it's a lot of careful design to create a block with like 4 different LUTRAM depth/width combinations

12:39 <Wanda[cis]> now, all of that may not seem like much logic, but the SLICE is already a pretty thin block of logic, so it adds a significant percentage

12:39 <Wanda[cis]> there's a reason Xilinx only makes like 25% of their LUTs into LUTRAMs

14:50 <azonenberg> Wanda[cis]: yeah i figured you wouldnt want to do *all* of your luts (although i assumed it was routing limitations not logic)

14:50 <azonenberg> more of a question of *none*