sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<jmabsd> Hi all, you know the BitBrick K1 RISCV SBC - how many PCI lanes do the two M.2 slots on the bottom get? And the miniPCI slot on the top get what?
<jmabsd> Their support support@youyeetoo.com monica@youyeetoo.com refer to their Wiki https://docs.bit-brick.com/docs/k1/k1-hardware/hardware-brief but I find it totally unclear
<jmabsd> Oh, their forum says it: It's one lane only. https://discourse.bit-brick.com/t/topic/43/2
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<jmabsd> Here is a thread about BitBrick K1's PCI performance, if anyone has anything to say please write up there: https://discourse.bit-brick.com/t/topic/47
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<jmabsd> I think few weeks ago someone here said the PCI performance on the BitBrick K1 isn't quite that great, but I don't remember details
<jmabsd> But subject to further Linux kernel / driver tuning.
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<kepstin> huh, i assumed the m.2 slots on the bottom of the bit-brick system would have been using two of the x2 pcie interfaces from the k1 soc.
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