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<diondokter[m]>
<JamesMunns[m]> RP2350 too
<diondokter[m]>
Ah! I thought maybe it was an M23
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<wassasin[m]>
NXP i.MX RT600 is also M33
<wassasin[m]>
cortex-m-rt has the set-msplim feature to check the stack limit on v8-mainline
<wassasin[m]>
* cortex-m-rt has the set-msplim feature to set the stack limit on v8-mainline
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<Mathias[m]>
NXP LPC55 has Cortex-M33 and has had Rust support for a while. Cortex-M33 are also in Nordic nRF5340/nRF91, ST STM32L5/STM32H5/STM32U5.
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<thejpster[m]>
<Noah[m]1> Are there people here using M33/M55/M85 cores already? With Rust. Are they any good? 🤔
<thejpster[m]>
No M55 or M85 hardware but I did analyse the machine code Rust produces in order to write the platform support page. Helium is incredible. The new loop instructions too.
<thejpster[m]>
I’ve seen one or two M55 parts - Renesas have one I think, but no M85 parts. There is also the Arm Fixed Virtual Platform (FVP) software - it emulates a whole virtual SoC using Arm’s own architecture models (the so called fast-models).
<RobWells[m]>
Does anyone know of a common SPI device that does full duplex communication (write to MOSI and read from MISO simultaneously)? I'm looking for something to test an implementation of eh::spi::SpiDevice::transfer against.
<Noah[m]1>
<wassasin[m]> cortex-m-rt has the set-msplim feature to check the stack limit on v8-mainline
<Noah[m]1>
ohh cool
<Noah[m]1>
<thejpster[m]> No M55 or M85 hardware but I did analyse the machine code Rust produces in order to write the platform support page. Helium is incredible. The new loop instructions too....
<Noah[m]1>
Oh sick! Wait Rust supports Helium?
<Noah[m]1>
Or rather LLVM
<Noah[m]1>
* rather LLVM I guess which makes sense
<diondokter[m]>
<RobWells[m]> Does anyone know of a common SPI device that does full duplex communication (write to MOSI and read from MISO simultaneously)? I'm looking for something to test an implementation of eh::spi::SpiDevice::transfer against.
<diondokter[m]>
[@tamme:matrix.org](https://matrix.to/#/@tamme:matrix.org) is there something you can share about the HAL testing project? Not sure if you've touched SPI yet
<RobWells[m]>
Thanks. Every SPI part I have is sequential write-then-read it seems. I misread the contract for transfer() initially (and implemented it sequentially) so it's mostly just to check I've got it right this time.
<whitequark[cis]>
<RobWells[m]> Does anyone know of a common SPI device that does full duplex communication (write to MOSI and read from MISO simultaneously)? I'm looking for something to test an implementation of eh::spi::SpiDevice::transfer against.
<whitequark[cis]>
nrf24l01
<whitequark[cis]>
as you shift in a command, it always shifts out status. and it's cheap
<RobWells[m]>
Great, thank you!
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<adamgreig[m]>
you could just short MISO and MOSI together I suppose
<adamgreig[m]>
and always read exactly what you transmitted
<RobWells[m]>
That's great, thanks Adam.
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