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<xypron>
Tartarus: Can we switch CI to QEMU 9.2.0? RISC-V support has evolved quite a bit since 8.2.0.
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<xypron>
Or better v9.2.3.
<Tartarus>
xypron: Yes, updating QEMU (post the evb-ast2600 situation) is on my list
<Tartarus>
ATM we're blocked because coreboot can't build from source because nasm.us is down
<Tartarus>
(And so I can't rebuild the docker container)
<xypron>
Tartarus: has DOGE taken it down
<Tartarus>
xypron: Someone else pointed out that yesterday was a big crackdown on all of the .us domains and zoom.us for example was down. It's unclear if nasm.us is down because of that too, or unrelated chnage
<xypron>
Tartarus: nasm is a package in Ubuntu. What do we need from nasm.us?
<Tartarus>
xypron: Because coreboot builds its own toolchain
<Tartarus>
That's the normal supported flow for it, using the system toolchain isn't advised
<Tartarus>
(And it's not a super trivial one line change, I told it to use it anyways and... it fails on some other part and I'm not yet motivated enough to look at say OE for how to build using the host toolchain fully instead)
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<soxrok2212>
marex: thanks, will dig in. cheers!
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<xypron>
Hello sjg1, as maintainer of buildman could you, please, decide which form of argument passing for multiple fragments we should adopt. It seems that taste differs. But in the
<xypron>
it only matters that we get to a decision.
<sjg1>
Tartarus: It is possible to build coreboot without its own toolchain. It makes no sense these days IMO
<soxrok2212>
marex: maybe you can point me in the right direction again RE this octeon board. it crashes in board_f.c at cpu_get_current_dev(). i think this is due to there being no cpu node in the device tree... octeon has a soc node instead.
<soxrok2212>
does u-boot have a precedence thing? I see there's a cpu.c specific to octeon in arch/mips/mach-octeon but i never seem to hit that logic
<marex>
soxrok2212: try and narrow it down to a specific line of code
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<Tartarus>
sjg1: Doesn't seem like it can be, at least if we also need to build coreinfo
<sjg1>
Tartarus: What is special about coreinfo? We don't need it though, if it is a problem. We are just building a coreboot.rom
<sjg1>
Tartarus: I can help look at something if you like
<soxrok2212>
ok, so its an ioread64 on ciu_fuse which is supposed to be a fuse that contains the number of cores. i can hardcode it, and it boots. but i need to figure out why that fuse is not right. doesnt help that i dont have the datasheet :/
<marex>
soxrok2212: oh good, so you did figure it out, nice
<soxrok2212>
yep!
<marex>
well done
<soxrok2212>
again, thanks for the help
<marex>
soxrok2212: dont forget to send patches
<soxrok2212>
once i figure out that fuse, sure
<soxrok2212>
any tips on that part, sans datasheet?
<marex>
soxrok2212: try and email the octeon maintain(s)
<marex>
well, try ioread32 ...
<marex>
if ioread64 faults on 32bit register, that might be it
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