ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.catirclogs.org/yosys/ | Bridged to #yosys:matrix.org
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<mkudinov> Hi guys! I've written a DVI display driver for Gowin FPGA a few months ago, and it was working with OSS toolchain just fine. I've managed to bisect the first bad commit in Yosys, but I'm not a programmer, so it gives me no clue. Basically after bad commit I don't have an image and display say 'out of range'. I don't know how to reduce my Verilog
<mkudinov> source to create a minimal example, cause I need a full DVI driver to see if it works. RTLIL diffs are also huge. How can I approach this?
<mkudinov> My code still works with proprietary Gowin IDE, so the problem is on Yosys side for sure. And changing the DVI DS pairs from registered to combinational solves the issue for some reason.
<lambda> what is the bad commit?
<mkudinov> lambda 23b3638c1e9a67c49e7e5f1208250c3e786da47a
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<whitequark[cis]> which commit is it?
<whitequark[cis]> one approach you could take is to split your display driver into individual modules, synthesize them one by one, and see if you can localize the problem that way. but this won't always work because sometimes the faulty transformation requires flattening to occur
<mkudinov> whitequark[cis] 23b3638c1e9a67c49e7e5f1208250c3e786da47a
<whitequark[cis]> oh, some messages got delayed/reordered
<mkudinov> but the problem is, if I don't synthesize the whole DVI, how would I know if it works or not?
<whitequark[cis]> you could synthesize some of the modules with the "good" yosys and some with the "bad" yosys
<whitequark[cis]> that being said, the commit you're pointing at has a bug fixed in the follow-up commit
<mkudinov> yeah, I know, I've checked the following commit as well, still broken
<mkudinov> I've been bisecting from Nov 28 till today, so I've checked a plenty of versions
<whitequark[cis]> interestingly, synth_gowin doesn't even run alumacc
<mkudinov> Do I understand correctly that in order to synthesize modules separately, I'll have to get verilog netlist with`write_verilog`, and then synthesize all netlists together?
<whitequark[cis]> oh wait it does, as a part of synth -run coarse
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<mkudinov> whitequark[cis] could you please elaborate how can I partially synthesize my design? If I separately synthesize a submodule, then include its netlist to the rest and synthesize top module, it gets synthesized again and the design doesn't work for some reason
<mkudinov> Is there a standard approach for partial synthesis?
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<whitequark[cis]> I would load all of them from RTLIL (read/write_rtlil) and flatten
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<mkudinov> But I have to synthesize top somehow to map it to FPGA cells
<mkudinov> Or I do regular synth after reading RTLIL and flatten?
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