<ydnatag[m]>
I think there is a bug in yosys for ecp5. rtlil is properly generated with all init attribute for all the cases (sgsr, async and sync resets) but looking at the .dot file, I'm seeing that there is no reset value for the flip flops
<whitequark[cis]>
is init value even reflected for FFs?
<whitequark[cis]>
if you can give a specific example of a netlist that contains an error and a description of the error that would help; it's not clear to me what problem you're reporting
<ydnatag[m]>
I think that yosys is not implementing properly the reset value of the register for ecp5
<ydnatag[m]>
In that code, I assigned init=1 to "signal_with_reset"
<ydnatag[m]>
And i tried 3 different types of reset:sgsr, sync and async
<ydnatag[m]>
And looking at the output of yosys, the init value is not anymore for the signal signal_with_reset
<ydnatag[m]>
(It is a ff)
<ydnatag[m]>
I was expecting to see a lut/mux driven by rst signal close to the ff because TRELLIS_FF only has LSR signal that sets a 0 to it.
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<ydnatag[m]>
I'm looking at the json instead of the .dot file and I think I'm completely wrong xD. I will test that code in hw and check the reset. if it is not the reset value I don't know what is happening in my design, outputs start in 0 instead of 1. Sorry for the noise
<benny2366[m]>
ok , that answers that part of the question, the first part of the question is apprantly running the "main" file . did that but did not see any vcd file being outputted
<conventia[m]>
This template shows how to do a blinky and simulate/synthesize it for the IceStick, VersaECP5 or TangNano. This should help with all your python questions, hopefully.
<benny2366[m]>
there arn't many diffrences , but then again that does not answer my question sadly enough
<benny2366[m]>
* many diffrences in my vs you'r code, but
<whitequark[cis]>
yes, you get output from it by just running it
<whitequark[cis]>
the .vcd file will be placed in your current working directory, in this case c:\users\benny
<whitequark[cis]>
s/:\/:\\/, s/\benny/\\bende/
<whitequark[cis]>
ah, you're also running the wrong file
<whitequark[cis]>
you should run buttontoled_TB.py
<benny2366[m]>
sorry?
<benny2366[m]>
AAAH ok it did run but was looking in the wrong place
<benny2366[m]>
and how does one let it place the vcb file in an other directory? ```with sim.write_vcd("C:\Users\bende\Documents\GitHub\amaranth_playground\buttontoled.vcd"):
<benny2366[m]>
``` i would think this would do the trick but it's complaining about unicodec somting something ``` ^
<benny2366[m]>
SyntaxError: (unicode error) 'unicodeescape' codec can't decode bytes in position 2-3: truncated \UXXXXXXXX escape```
<galibert[m]>
\ has a meaning in python strings. As Cat said, using amaranth requires knowing python
<whitequark[cis]>
to put a backslash to a string in python you have to escape it as \\, or use a "raw string" with the following syntax: r"c:\users\whatever"
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<catimor129[m]>
not converged: 1147985 (delta_cycles) am i cooked? should i be looking for some comb cycle?
<whitequark[cis]>
yes
<whitequark[cis]>
if you convert to verilog or rtlil, we have a static checker that will point you to the comb cycle
<whitequark[cis]>
unless the cycle involves a testbench/process in which case you'd have to do it manually
<catimor129[m]>
yes testbench and a bunch of processes, thanks. sleep first 😢