00:35
_whitelogger has joined #glasgow
01:20
Emantor has joined #glasgow
02:47
redstarcomrade has joined #glasgow
03:03
redstarcomrade has quit [Read error: Connection reset by peer]
03:10
smkz has quit [Quit: smkz]
03:11
smkz has joined #glasgow
03:13
redstarcomrade has joined #glasgow
03:13
redstarcomrade has quit [Changing host]
03:13
redstarcomrade has joined #glasgow
05:36
redstarcomrade has quit [Read error: Connection reset by peer]
05:48
GNUmoon has quit [Remote host closed the connection]
05:49
GNUmoon has joined #glasgow
06:48
mobius has quit [Ping timeout: 245 seconds]
06:49
mobius has joined #glasgow
12:16
FFY00_ has quit [Read error: Connection reset by peer]
12:16
FFY00 has joined #glasgow
12:20
FFY00 has quit [Remote host closed the connection]
12:20
FFY00 has joined #glasgow
13:13
Eli2 has joined #glasgow
13:14
Eli2| has quit [Ping timeout: 272 seconds]
13:45
redstarcomrade has joined #glasgow
13:45
redstarcomrade has quit [Changing host]
13:45
redstarcomrade has joined #glasgow
14:40
<
galibert[m] >
Catherine: available?
15:09
<
whitequark[cis]1 >
yes?
15:09
<
galibert[m] >
I am looking at gateware/i2c.py
15:09
<
galibert[m] >
I assume you want to converted to components
15:09
<
galibert[m] >
s/to/it/
15:10
<
galibert[m] >
But I'm not sure what you'd like the signatures to look like
15:10
<
galibert[m] >
(locally, i2c-initiator by itself works as V2 afaict)
15:11
<
whitequark[cis]1 >
I want to rewrite it some later time, the existing gateware is fine for the time being
15:11
<
galibert[m] >
Ok then
15:11
<
galibert[m] >
I'll go on poking at the inheritance then
15:13
<
whitequark[cis]1 >
what i did with the SPI controller is to make an exact copy of the old applet, unlisted in `glasgow run`
15:16
<
galibert[m] >
no sure it's needed honestly, the conversion seems to be sane
15:19
<
whitequark[cis]1 >
well, it's a way to get it merged faster, since i do want things to be tested
15:20
<
whitequark[cis]1 >
(for at least some of the applets, adding HIL tests is in order too)
15:21
<
galibert[m] >
so you'd rather have a copy with V1 appended and have the inheritance done on that one, and then we can convert those one by one?
15:28
<
whitequark[cis]1 >
that seems to be the sustainable long term path yes
15:28
<
galibert[m] >
no problem, I think :-)
15:29
<
whitequark[cis]1 >
<galibert[m]> "so you'd rather have a copy with..." <- not quite the same as you say though, look at what i did for SPI and copy it
15:33
<
galibert[m] >
is that spi_controller_deprecated?
15:33
<
whitequark[cis]1 >
yeah
15:33
<
whitequark[cis]1 >
intentionally obtuse and long
15:34
<
galibert[m] >
hmmm, you have the name SPIControllerApplet for both? I wouldn't have thought you'd do that
15:36
<
whitequark[cis]1 >
good point actually, I think what I did was to do an IDE rename on the module alone to minimize the diff
15:36
<
whitequark[cis]1 >
but I'm fine with it being confusing since that's all the more motivation to migrate everything
15:37
<
galibert[m] >
It's a choice :-) I tend to be a little paranoid about that
15:38
<
whitequark[cis]1 >
I mean, normally this would be grounds to immediately fix it
15:39
<
whitequark[cis]1 >
but I don't want to encourage keeping around obsolete unsupported code any more than I absolutely have to
16:29
itsmk has quit [Quit: moving]
16:43
<
whitequark[cis]1 >
galibert: once all the surface level stuff is fixed i'll go through the actual code of the PR
16:44
<
galibert[m] >
Good. Sorry for messing up the analyzer stuff, I forgot it was there at the critical time
16:44
itsmk has joined #glasgow
16:47
<
whitequark[cis]1 >
i usually use branches
16:48
<
galibert[m] >
I'm not too used to work in one directory only. My branches tend to be independant directories
16:58
redstarcomrade has quit [Read error: Connection reset by peer]
17:02
<
galibert[m] >
add_clock_divisor computes the divisor, it does not create any gateware, right?
17:03
<
whitequark[cis]1 >
it does
17:06
<
galibert[m] >
through the AbstractRWRegister?
17:06
<
whitequark[cis]1 >
take a look at how the SPI applet does it
17:06
<
galibert[m] >
the idea is that you can change it anytime from the host side?
17:06
<
whitequark[cis]1 >
yes, it creates a register, and yes
17:07
<
whitequark[cis]1 >
what it also does is takes care of doing the frequency/cycle count conversion
17:07
<
galibert[m] >
It's more of a ClockDivisorFactory than a ClockDivisor :-)
17:07
<
galibert[m] >
I mean it does everything but dividing the clock
17:09
<
whitequark[cis]1 >
it's meant as a noun
17:09
<
whitequark[cis]1 >
"the clock divisor is 2"
17:10
<
whitequark[cis]1 >
(and the factory here is the assembly. actually, the entire point of AbstractAssembly is to be an Everything Factory)
17:10
<
galibert[m] >
I hadn't noticed the Abstract*Register, nice concept
17:11
<
whitequark[cis]1 >
yes, it's needed because I don't want to simulate the I2C dance (or the FX2 itself for that matter)
17:11
<
whitequark[cis]1 >
the concept I'm using for glasgow.abstract is called "dependency injection"
17:12
<
whitequark[cis]1 >
a "factory" is how you often implement "dependency injection"
17:12
<
galibert[m] >
ah yeah, there's also that. But it makes communicating with an applet outside of a stream way nicer, I really like it
17:13
<
whitequark[cis]1 >
oh, we always had registers (i implemented them before i added FX2 FIFO support)
17:13
<
whitequark[cis]1 >
it's just that the pre-assembly API for them was ... bad
17:13
<
galibert[m] >
yeah, I just hadn't noticed them yet :-)
17:13
<
galibert[m] >
feels like V2 is a real step forward, compared to when I first tried.. I'm not sure how long ago, when I got the glasgow
17:14
<
whitequark[cis]1 >
yes, it's a major part of what will make it possible to have a stable, documented API and an applet tutorial
17:14
<
whitequark[cis]1 >
which is why I pushed so hard for it recently
17:56
<
galibert[m] >
hmmm, implementing the divier the correct way will require changing the gateware which will make it incompatible with the previous version
17:57
<
whitequark[cis]1 >
oh, hm.
17:57
<
whitequark[cis]1 >
tell me more?
17:57
<
galibert[m] >
class I2CInitiator(Elaboratable):
17:57
<
galibert[m] >
def __init__(self, pads, period_cyc, clk_stretch=True):
17:57
<
galibert[m] >
self.period_cyc = int(period_cyc)
17:58
<
galibert[m] >
timer = Signal(range(self.period_cyc))
17:58
<
galibert[m] >
with m.If((timer == 0) | ~self.busy):
17:58
<
galibert[m] >
m.d.sync += timer.eq(self.period_cyc // 4)
17:58
<
whitequark[cis]1 >
okay, yeah, i see
17:58
<
whitequark[cis]1 >
in the interest of keeping it manageable, let's keep the divisor fixed, even if it's fairly ugly
17:59
<
galibert[m] >
probably can force timer size to 16, plonk the divider in the interface and have the upper plonk a C(computed value) there
17:59
<
galibert[m] >
that should stay very small
17:59
<
galibert[m] >
the // 4 becomes a slice, nothing big
17:59
<
whitequark[cis]1 >
nah, don't bother; i'd rather keep this particular gateware the way it currently is
18:00
<
whitequark[cis]1 >
i plan to implement a new stream-based I2C controller anyway
18:00
<
galibert[m] >
but then I can't use ClockDivider
18:00
<
whitequark[cis]1 >
yeah
18:00
<
galibert[m] >
ok then
18:00
<
galibert[m] >
we can do that later
18:00
<
whitequark[cis]1 >
ignore that part of the review
18:00
<
galibert[m] >
works
18:00
<
galibert[m] >
I like the way you do clocks now though I must say :-)
18:01
<
whitequark[cis]1 >
yes, it's a significant improvement
18:01
<
whitequark[cis]1 >
i trialed a few solutions some years ago but none of them were very good
18:01
<
galibert[m] >
so use_pulls is the last missing piece
18:03
<
galibert[m] >
later though, RL stuff to do now :-)
18:05
redstarcomrade has joined #glasgow
18:05
redstarcomrade has quit [Changing host]
18:05
redstarcomrade has joined #glasgow
18:51
redstarcomrade has quit [Read error: Connection reset by peer]
19:02
twix has joined #glasgow
19:41
whitequark[cis]1 has quit [Quit: Reconnecting]
19:41
whitequark[cis] has joined #glasgow
20:04
redstarcomrade has joined #glasgow
20:04
redstarcomrade has quit [Changing host]
20:04
redstarcomrade has joined #glasgow
22:31
Foxyloxy has joined #glasgow
22:32
redstarcomrade has quit [Read error: Connection reset by peer]
22:34
tomkeddie[m] has quit [Quit: Idle timeout reached: 172800s]
22:49
tec4 has quit [Quit: bye!]
22:51
tec4 has joined #glasgow
23:19
redstarcomrade has joined #glasgow