10:30 <xypron> sjg1: 91bc909d317c ("spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V") addressed the same issue for other configruations. We should generally increase the value to 8 MiB on RISC-V boards. This should be good enough to include FPGA blobs or splash images in future. See defconfigs for RISC-V Xilinx boards and the StarFive VisionFive 2.

10:43 <xypron> sjg1: https://lists.denx.de/pipermail/u-boot/2025-May/590567.html

10:48 <sjg1> xypron: OK thanks

15:16 <Tartarus> Sigh, https://docs.readthedocs.com/platform/stable/guides/environment-variables.html and so I've set PYTHONPATH via the dashboard, but it wasn't used in rebuilding a previous commit. So next up, once I merge xypron's PR to master maybe that will pick it up

17:50 <sjg1> xypron: Wow I just read that properly - 8M in SPL!! Gosh, times have changed

17:55 <xypron> I can't see any RISC-V board using SPL that does not have at least 64 MiB of RAM.

17:56 <xypron> So allowing 8 MiB for SPL malloc should not be problematic.

17:57 <sjg1> xypron: Hmmm, I recall your slides about the boot process, with SPL being before Tianocore in some cases. Where is the DRAM setup?

17:58 <xypron> Either before SPL (e.g. SiFive HiFive Premier P550) or in SPL.

17:59 <xypron> There is a separate Kconfig value for early malloc which may have to fit into the cache.

18:01 <sjg1> xypron: OK, got it, thanks