whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<adehop> Hi! I'm tinkering with a GateMate FPGA and wanted to try the OSS CAD Suite for PnR but i can't figure out how to create a bitfile for programming (Olimex board). All i was able to generate was a textconfig file but i don't know how to get a bitstream from that for GateMate. May anyone help me with this?
<adehop> Or is it possible to use the textconfig file as an input for openFPGALoader? Till now i worked with ECP5 and used ecppack to get a binary bitfile which i used with openFPGALoader.
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<lofty[m]> adehop: you use the textconfig with openFPGALoader.
<lofty[m]> ...correction: you use gm_pack from prjpeppercorn, and then use that with openFPGALoader
<lofty[m]> I am still kind of asleep, sorry
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<adehop> Thank you. Is gm_pack part of the OSS CAD Suite (couldn't find it in the recent release)? The other tools needed (yosys + nextpnr-himbaechel) were in the current release.
<adehop> Now as you mention it, i found https://github.com/YosysHQ/prjpeppercorn-test-cases/blob/main/makefile.inc where i see how it's intended to be used.
<adehop> I just wonder how to get it - do i need to compile it myself?
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<lofty[m]> Yes
<adehop> Thanks for the hint :-)
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<Semisol[m]> <famubu[m]> "I have a small verilog file that..." <- > <@famubu:matrix.org> I have a small verilog file that I synthesized with yosys.... (full message at <https://catircservices.org/_irc/v1/media/download/ARPCsXp-UnRssyWHYt7UFXDSppKPMCuQSeEFD2rfXrPRrDWGrNxnnkD7_a8hBpOADDNHIJ3vJzgw5J9cP90IbwW_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9LWEF6U0pTZElBamlrc0NMU2xabFFXWlI>)
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<adehop> lofty[m] Thanks again for the hint towards prjpeppercorn, was able to build gmpack myself and program the board. Do you know why gmpack/gmunpack is missing in the OSS-CAD-Suite Release?
<lofty[m]> the tooling isn't mature enough to include it at the moment
<adehop> Ok, so no issue but intended. I recognized routing also takes quite long compared to the CologneChip tools. Meeting CC at Embedded World they said that they actively help the OSS community. Would be great for the project.
<adehop> Do you know what the concerns are about? Could the configuration damage the FPGA?
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