whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<lofty[m]> <adehop[m]> "lofty: Not yet, i gave it a..." <- to be entirely honest most of the options are debug tweaks, where the average user probably doesn't need to bother too much with them
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<whitequark[cis]> danderson: there isn't really a great place to document these things, unfortunately
<whitequark[cis]> it might end up having more visibility under your blog (in terms of discoverability by actual user behavior, i.e. search engines mostly) than deep in the guts of prjtrellis or something
<whitequark[cis]> and i don't think anybody looks to yosys for vendor primitive documentation
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<danderson> hmm, okay so I didn't miss a cache of "how to use $fpga_model with the yosys ecosystem" docs then. I'd be up for putting one of those together, at least for ECP5 and maybe iCE40 since those are the ones I have
<danderson> but in the meantime the blog's not going anywhere, so that's fine too
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<danderson> on a related note, https://github.com/YosysHQ/nextpnr/pull/1475 fixes nextpnr timing constraints for an esoteric PLL configuration :)
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<tnt> danderson: I put some info about ice40 on the icestorm github wiki ... not great but I also didn't know where to put it .
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<adehop[m]> <lofty[m]> "to be entirely honest most of..." <- No problem, it's absolutely relatable to use them as Dev at this development stage. So i just use "--router router2" for my design. Recent problem is that in releases as of April 24 and 25 there were timing issues (ERROR: Hold/min time violation) reported. In releases as of April 28 and 29 it does not even get that far, step "Running main analytical placer" hangs at iteration #24. In the
<adehop[m]> older releases it took 16 iterations to finish this successfully (but to fail later with the mentioned timing issues).
<adehop[m]> Should i just wait for newer releases or is this something to investigate further at this point? The design successfully runs in the GateMate using CologneChip p_r and also in an ECP5 (nextpnr-ecp5) and various Xilinx devices (actually using Vivado).
<lofty[m]> <adehop[m]> "No problem, it's absolutely..." <- we're getting there; over the next few months we'll invest time into improving the overall flow, and hopefully resolving the hold time violations. (I can explain those if you really want.)
<lofty[m]> (also, I should mention that gm_pack et al are now in OSS CAD Suite)