18:16 <ydnatag[m]> Is there any way to get a signal that is not driving any other part of the design and will be pruned by synth? I'm having a problen that synplify pro is pruninng a part of my design (breaking a cdc false path contraint) and i'm not finding what is unconnected

18:27 <whitequark[cis]> sorry, can you rephrase that?

18:30 <ydnatag[m]> Yes, sure. Synplify pro is pruning part of my design and breaking pnr because a net has a false path contraint and does not exist anymore after synthesis. So i need to find out where the synthesizer started pruning my design. In other words, where i left a net not driving any logic or port.

18:34 <ydnatag[m]> I was looking at logs but i was not able to find the net. So my question is if amaranth has a way to get signals that are in the design but are not driving any other signal.

18:35 <galibert[m]> Define « get »

18:43 <ydnatag[m]> Hmmm... i think it would be grest to get the ful path of the signal in the design, like top.fifo.consume_cdc.stage0. But having the object i can get the path to the signal with the SignalDict name_map

18:43 <whitequark[cis]> jethromightbemydad: not currently, unfortunately, and signals in Amaranth have more than one full path

18:43 <whitequark[cis]> however, if you look at the NIR (the internal Netlist class), you should be able to devise a way to get it

18:44 <whitequark[cis]> right now I don't have the space in my life to write you a complete solution but hopefully this pointer will help you

18:53 <ydnatag[m]> No problem! I was no expecting a complete solution neither xD. I'm just asking you because I was trying to solve this issue for a long and I'm a little bit frustrated, but i will find out the issue. Thank you for you time and help.

18:53 <ydnatag[m]> The main problem I have is that I'm using amaranth to generate a project for the polarfire. I think that you know how bad libero is hahah

18:57 <whitequark[cis]> I actually don't have libero installed somehow

19:07 <ydnatag[m]> It is the worst sw i've ever used. And for old devices like proasic or smartfusion is even worse.

19:09 <ydnatag[m]> I'm a little bit surprised that amaranth does not have support for any microchip, i thought it was because of libero

19:11 <ydnatag[m]> * any microchip device, i

19:25 <whitequark[cis]> no, nobody just expressed any interest in it

19:25 <whitequark[cis]> I'm generally fairly proactive about adding new toolchains, and Amaranth probably has the most integrations of any HDL in existence (not including specialized tools like FuseSoC)

19:31 <ydnatag[m]> That is why i was surprised, know your effor to include as much vendors as possible.

19:31 <ydnatag[m]> I can't open the integration i've done because i'm not allowed u.u. but the main problem i had was the initialization value for memories. Synplify pro that comes with libero does not support inline memory initialization and must be done using a text file and use verilog file functions :/.

19:49 <whitequark[cis]> ohhhhh, that problem

19:50 <whitequark[cis]> this problem has been a thorn in my side for years, and unfortunately it's quite tricky to do anything about it

19:50 <whitequark[cis]> I've hit it with Diamond too, it is currently unsolved

20:08 <ydnatag[m]> I solved it in a very nasty way with regex. Looking for memory initialization, extracting the data and raplacing it with the supported syntax... I'm not really proud of it, but works

20:10 <whitequark[cis]> tbh not the worst solution, the "better" alternatives involve so many cross-cutting hacks across so many projects that it's still not upstream