<AhmedCharles[m]>
How easy would it be to add a warning when a signal gets truncated? Like Signal(4).eq(Signal(8)).
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<whitequark[cis]>
there's an open issue for it I think. we could add a per-file-enabled warning for it
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<AhmedCharles[m]>
Thanks, I'll look for it.
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<jorolf[m]>
What would be a good way to check if a stream transmitted all its data as expected? I was thinking about using something like crc or md5 where I can just check a number at the end
<jorolf[m]>
But CRC (probably?) doesn't catch out of order payloads and there's no md5 or similar implementation in the stdlib
<zyp[m]>
CRC absolutely catches out of order payloads
<jorolf[m]>
Oh hmm okay, I got a bit confused by the online explanations
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<RowanG[m]>
What do you mean with "catches"? As in you get the same CRC for the out of order payload as the in order payload?
<RowanG[m]>
Or the other way around
<jorolf[m]>
Ah, I meant that payloads that are delivered in the wrong order should result in a different check value
<RowanG[m]>
Because let's be clear. If you do CRC(a, b, c) and CRC(b, a, c)
<RowanG[m]>
then you get a different CRC value
<RowanG[m]>
oke, yes then you can use CRC for that.
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<ydnatag[m]>
is there any plan to support "parameter"? I mean, using amaranth to generate IP cores is really usefull but not everyone wants to use it, so It would be great to support verilog generation with parameters.
<zyp[m]>
how would that work?
<ydnatag[m]>
I work with several customers that don't want python. So I run the verilog generation in my computer and send them the file. The problem is that, for each configuration/parametrization, they ask me for a new one
<ydnatag[m]>
About amaranth code, I have no idea or proposal about how to treat that
<ydnatag[m]>
I would like to have the possibility to do something like: Signal(Parameter())
<ydnatag[m]>
hmmm... destroying an idea just with just one question ahahah
<ydnatag[m]>
you are right
<ydnatag[m]>
I didn't think about that. It would work only for a sub set of operations
<zyp[m]>
for simple cases like that, you could probably also just tie off signals to constants and rely on constant folding
<zyp[m]>
e.g. just make the signal as wide as the widest supported case, and tie off the unused bits
<zyp[m]>
you could even wrap the amaranth generated module in a parameterized verilog shim that does it for you
<zyp[m]>
parameterization that constant folding and dead code elimination can't deal with is probably parameterization that you'd really want to handle in python before elaboration anyway
<ydnatag[m]>
Sounds insteresting. That would work for mostly of the use cases I need.
<ydnatag[m]>
That helps me a lot, Thanks
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