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<_whitenotifier-a>
[glasgow] joelpmichael closed issue #1007: Off-By-1 error in glasgow.gateware.clockgen.ClockGen causes incorrect clock frequency to be generated - https://github.com/GlasgowEmbedded/glasgow/issues/1007
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<altracer[m]>
CM0+ has DWT, but it does not have ITM/SWO of CM3. Any debugger can poll DWT_PCSR, even a BMP, at 10 kHz realistically, as ersatz orbtop-style PC-sampling, I recorded a couple commits trying to implement that.
<altracer[m]>
indulge in Segger SystemView and instrument every primask-touching callsite, to record into ringbuffer of RTT, dump later (instrumenting IRQ in baremetal is standard practice there)
<altracer[m]>
Glasgow could be a simple MEM-AP poller unidirectional pipe for select few registers, and USB HS kinda lets you annotate every access I think (limited by SWCLK not USB)
<tpw_rules>
standard practice where?
<altracer[m]>
in SystemView usage
<tpw_rules>
ahh, yeah i am not that rich
<tpw_rules>
but i was considering doing something similar
<altracer[m]>
"evaluation" to see how industry does it, reimplement if you don't like it
<tpw_rules>
another idea i had to sort of do it "deployed" was to have a periodic NMI
<tpw_rules>
rp2040 can fire an nmi from a timer
<altracer[m]>
likely there's some stupid atomic section with primask because armv6-m doesn't provide other ways (armv7-m ldrex+strex, basepri, etc.)
<tpw_rules>
but i'm not quite that desperate and the project isn't quite that desperate
<tpw_rules>
yeah i'
<tpw_rules>
ve found a few
<tpw_rules>
but (un)fortunately the issue is now getting much rarer
<tpw_rules>
i really do wonder why rpi souped up an m0+ so much for the rp2040. maybe they didn't want to pay the licensing
<altracer[m]>
if you're on rp2040, force the second core poll state of first core via mutual debug, that's inherently faster than SWD
<tpw_rules>
i'm not quite sure what you mean. i did see that register to frob the SWD lines from software
<altracer[m]>
or push DWT_CYCCNT to mailboxes strategically
<tpw_rules>
do i need to find the cortex m0+ debug access point manual?
<tpw_rules>
in the diagrams in the datasheet i don't see any debug connection between the cores except SWD
<tpw_rules>
(fwiw it also says max SWD frequency of 24MHz which would presumably also apply to the second core)
<altracer[m]>
ah no, only rp2350 has loopback mapping of debug APB-AP, on rp2040 you indeed can only force bitbang own SWD pins
<tpw_rules>
i see, thanks. so i also gather that CMSIS-DAP and USB are not rated for 10KHz polling, i would need an intelligent debugger somehow anyway right
<whitequark[cis]>
to hit more than 8 kHz you'd need to get a packet per microframe
<whitequark[cis]>
this is... not totally impossible but rather optimistic to do reliably
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