05:01 <CounterPillow> how would you know anything about the performance of something with unannounced Arm cores

10:03 <diederik> Wow, I would've expected a bit more positive feedback to a new chip :-O

10:34 <robmur01> TBH I'd fully expect any near-future RK SoCs not to outperform Cix P1, for the simple reason that the latter is firmly targeted at the desktop PC market, whereas RK focus on embedded (mostly Andriod) markets

10:41 <phh> Dex2x: https://www.cnx-software.com/2025/07/18/rockchip-unveils-rk3668-10-core-arm-cortex-a730-cortex-a530-soc-with-16-tops-npu-rk182x-llm-vlm-co-processor/ 8x A730 + 4x A530 (not seen in the text only in the photo)

10:42 <phh> 200gb/s lpddr6

10:44 <diederik> robmur01: so due to thermals? But a board like the 5 ITX shouldn't have that problem?

10:47 <CounterPillow> diederik: no

10:47 <CounterPillow> due to the picked core IP

10:48 <robmur01> diederik: not just thermals, I mean the whole design - cache sizes, interconnect, etc.

10:48 <diederik> ok, thanks

10:51 <robmur01> Consider that 4 cores worth of Graviton2 would probably wipe the floor with RK3588, despite the N1 and A76 CPU cores being more or less the same design at heart.

11:01 <diederik> I think I understand :-) So it's basically what CounterPillow said. And my first question probably wasn't that far off the mark, except those considerations affect the whole SoC design (and therefor selected IP), so it's much 'deeper' then I initially thought

11:04 <Dex2x> phh, I was looking at the TOPS of the CPU compared to the one the radxa orion 6 uses

11:09 <CounterPillow> that's NPU tensor operations

11:09 <CounterPillow> aka dead silicon

11:26 <robmur01> my made-up number is bigger than your made-up number, I am clearly better in every regard

11:30 <Ermine> proper benchmarking is hard

11:34 <robmur01> and unless an NPU can run GCC then has no bearing whatsoever on my notion of performance :)

11:36 <robmur01> *it has

11:40 <phh> well some people like to run games, and i don't think gcc has mali target?

12:15 <robmur01> Even for games, a number for how many matrix multiplications the NPU, GPU and CPUs could theoretically all perform at the same time (disregarding power budgets) is hardly meaningful

12:16 <phh> yes but it's a far cry from "if i can't target it in gcc it's useless"

12:28 <robmur01> Did you miss the word "my" in that sentence? *I* am a software engineer; I spend a lot of time compiling stuff. *My* overwhelming measure of "performance" is how fast a system can compile stuff, i.e. I/O bandwidth, memory bandwidth and CPU integer throughput

13:46 <Dex2x> robmur01, did you see the new threadripper?

14:18 <CounterPillow> It's like I'm really conversing with a YouTube clickbait thumbnail, impressive technology.

14:23 <Ermine> is it expected that I can't read device's partition table through rkdeveloptool until I load SPL?

14:26 <diederik> I believe so. I think there may be a situation where it's not needed, but I haven't figured out how/when. But if you test the device and you're not getting "OK", then you need to load (ie "boot") SPL in order to work with the device

14:31 <CounterPillow> Ermine: yes

18:25 <warpme_> guys: what is status of uboot booting from ufs on rk3576? Is there any uboot branch supporting this?

18:26 <CyReVolt> https://github.com/rockchip-linux/rkbin/blob/f43a462e7a1429a9d407ae52b4745033034a6cf9/LICENSE#L19

18:26 <CyReVolt> I guess I should ask someone at Rockchip about translating their binaries to Rust. 🤔 Is anyone here in touch with them by the chance? 😬

18:27 <CyReVolt> ah crap, multiline message, sorry

18:28 <CyReVolt> https://github.com/rockchip-linux/rkbin/blob/f43a462e7a1429a9d407ae52b4745033034a6cf9/LICENSE#L19 I guess I should ask someone at Rockchip about translating their binaries to Rust. 🤔 Is anyone here in touch with them by the chance? 😬

18:29 <CyReVolt> I see diederik: 's PR has been open for months, so I assume opening an issue may remain answered for a longer while as well, maybe forever. I would also prefer asking non-publicly first.

18:32 <CounterPillow> would be a bit hard for them to enforce that clause when their binary is just U-Boot TPL in a trenchcoat

18:34 <jakllsch> who needs memory safety when you don't have DRAM yet :-P

18:37 <Ermine> if it would reduce the number of bugs it would be nice. I've stuck upon a bug yesterday

19:16 <diederik> I only later realized they don't merge PRs. The ones that were previously opened were all closed by the author ... because they never got a reply

19:17 <diederik> But hopefully it'll help anyone else who runs into the same problem I did