whitequark[cis] changed the topic of #prjunnamed to: FPGA toolchain project · rule #0 of prjunnamed: no one should ever burn out building software · https://prjunnamed.org · https://github.com/prjunnamed/prjunnamed · logs: https://libera.catirclogs.org/prjunnamed
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<vancz> RobTaylor[m]: thanks ill take a look
<vancz> whitequark[cis]: see the end of https://bpa.st/WQCA
<vancz> Sorry, my code is messier than it needs to be
<whitequark[cis]> <vancz> "Catherine: see the end of https:..." <- run cxxrtl_outline_eval once per step on each unique outline field
<whitequark[cis]> (right now i only generate one outline per design, but this may change in the future)
<whitequark[cis]> this will regenerate the values of all optimized out signals (which you can tell were optimized out by the flags)
<whitequark[cis]> it'll also of course make the simulation slower, so adding cxxrtl_keep might be a better option in some cases (or just making it a toplevel output)
<vancz> ok i see the commend in the cxxrtl_capi.h file
<vancz> comment
<whitequark[cis]> basically the point of cxxrtl is that you have values for every signal with a public name (and state holding signals with private names) at all optimization levels, but it also doesn't force you to calculate them at all times
<vancz> So like, putting cxxrtl_outline_eval(s->led->outline); at the end of do_clk?
<vancz> Seems to work.
<whitequark[cis]> yep
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