00:06 <DemiMarieObenou4> Given the input & output of a P&R tool, how difficult is it to check that the output is correct? If it is easy to check that the output is correct, I wonder if a machine learning model could be used.

00:07 <whitequark[cis]> it's easy to check that the output is correct. and yeah, people have been doing ML-driven P&R for a while

00:07 <whitequark[cis]> synthesis too, with pathetic results

00:08 <DemiMarieObenou4> whitequark[cis]: Is it any faster/better/etc than the traditional way?

00:08 <whitequark[cis]> far as i can tell it's just a fad

00:09 <DemiMarieObenou4> Are the results garbage? I couldn’t tell if “with pathetic results” only applied to synthesis or to P&R as well.

00:10 <whitequark[cis]> synthesis, where it's like... only occasionally correct at all

00:11 <DemiMarieObenou4> whitequark[cis]: Is that because it has no advantages over standard P&R?

00:13 <whitequark[cis]> it doesn't seem practical enough for any major vendor to use it

00:14 <DemiMarieObenou4> I wonder if the immense amount of work put into ML would make things better now.

00:23 <RobTaylor[m]> Maybe placement (I have a collection of interesting papers for ASIC placement, padring, and pinout) but I very much doubt routing. You could have some mileage by providing a model with a routing tool and a tool to understand the graph of the design and using it to vary parameters.

00:23 <DemiMarieObenou4> Which one is slower in practice?

00:23 <RobTaylor[m]> Sorry I don’t understand the question

00:25 <DemiMarieObenou4> Which step of P&R takes more time?

00:28 <whitequark[cis]> routing takes a lot more, usually

00:29 <RobTaylor[m]> Yeah routing by far. It’s iterated until completion

00:54 <RobTaylor[m]> Demi Marie Obenour: David Z. Pan's team at utexas has done some investigation, worth reading through their papers.

01:19 <ignaloidas> About routing on larger spaces being easier - from experience with Factorio belt balancer finding using SAT (it's honestly not that different from a very, very small scale P&R), for the same "circuit", only the sizes at the limits of where it's possible to fit them get slow, if you bump it so it's like 20% more space, you get as results as fast as you're gonna get, more room will just take more time to express and slow you down a very small

01:19 <ignaloidas> amount

06:51 <galibert[m]> isn't placement also iterated until completion? I thought it was using annealing or something similar

14:00 <vancz> i just remembered logisim or what also has HDL synthesis

16:20 <vancz> today, attempt number 3 at trying to get myself to do something with serv. I have copy pasted the demo commands in the readme, way to go me.

16:30 <vancz> can I get a nudge?

16:30 <vancz> So given that I'm primarily interested in hooking up MMIO, and clock in, I guess I want the Serving implementation?: https://serv.readthedocs.io/en/latest/reservoir.html

16:30 <vancz> and then one more thing I need to do is figure out what to do about the timer interrupt to make serv/zephyr happy

16:32 <vancz> derp, I think I actually want to hook up the Mem interface in the top right of the diagrams

16:33 <vancz> AFAIU "RF" is the internal registers?

16:33 <vancz> "and an RF interface for connecting to an SRAM for GPR and CSR registers."

16:33 <vancz> so I just want that to be part of the RTL model

16:37 <vancz> ok RF is Register File not radio frequency (well, registers are fast I guess?)

16:51 <vancz> so, I probably dont care about Data(?)/gpio since right now everything is MMIO. I dont care about RF and want it to be internal. I do care about Mem.

16:54 <vancz> I guess I could try just cannibalizing a Servant example and exposing the ram lines