whitequark[cis] changed the topic of #prjunnamed to: FPGA toolchain project · rule #0 of prjunnamed: no one should ever burn out building software · https://prjunnamed.org · https://github.com/prjunnamed/prjunnamed · logs: https://libera.catirclogs.org/prjunnamed
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<vancz> kinda wonder if this whole thing is fundamentally misguided not following standard verification flow or something though
<vancz> whitequark[cis]: i have not developed a taste in protocols yet, why is it bad?
<whitequark[cis]> inefficient, quirky for no reason, poorly suited for the task at hand
<zyp[m]> and legacy stuff stacked on top of legacy stuff
<vancz> ok debugger mostly works, now i need breakpoints
<vancz> oh and to figure out how to dump the register file i guess... though not strictly necessary...oh and detecting hardware exceptions...
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<vancz> ok cool i can (kind of) start/stop vcd dumping from the debugger
<vancz> would be cool if gtkwave was extensible...
<vancz> i havent tried to build azonenberg's thing yet
<azonenberg> vancz: ngscopeclient right now needs some work to be usable for hdl debug stuff
<azonenberg> in particular we don't have great support for digital vectors
<azonenberg> that's been a long standing todo and one i hope to revisit soon as i work on building out a flow from an FPGA ILA to ngscopeclient
<vancz> would be cool to populate the value labels for the instruction bus reads with disassembly
<azonenberg> i have a lot of fun ideas for things like that
<azonenberg> i want to be able to decode APB/AXI bus traffic in a simulation or ILA capture and go up to register names
<azonenberg> etc