sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<meowray> are there use cases for the alternate link register x5? machineoutliner?
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<jrtc27> meowray: -msave-restore
<jrtc27> which I guess is kind of just a very inflexible outliner
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<meowray> jrtc27: thx. i asked as i stumbled across the weird condition used by Zicfilp (CFI) is_lp_expected = ((JALR || C.JR || C.JALR) && (rs1 != x1) && (rs1 != x5) && (rs1 != x7) ) ? 1 : 0; // the != x5 and != 7 clauses make me sad
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<mfny_> so ive ordered a P550
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