sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<drewfustini> Palmer: have you seen any discussion since this two years ago? https://lore.kernel.org/linux-riscv/mhng-6bb8dac2-33c3-410f-82ce-36554e497e9c@palmer-ri-x1c9/
<drewfustini> We've noticed that null syscall latency takes a hit because of it
<drewfustini> Maybe it could be made optional?
<palmer> drewfustini: if you have a benchmark on HW then just send a patch to turn it off (maybe some DT key for performance?)
<drewfustini> Bjorn
<drewfustini> Oops
<palmer> I haven't heard anything else I can quote ;)
<drewfustini> Okay yeah I'll work on getting some public data
<palmer> Thanks. It's not surprising it's going to be a perf problem, we just need something concrete
<drewfustini> > DT key for performance
<drewfustini> Do you mean creating a device tree property regarding this performance aspect?
<palmer> Ya, there's going to be some microarchitectures it's slow on
<palmer> There might also be some other zeroing scheme you need, or whatever
<drewfustini> Okay, I'll post some data
<drewfustini> Thanks
<palmer> Cool, thanks
<palmer> We're pretty far into microarchitecture specific stuff here, so it's impossible to tell exactly what's the right answer -- just that some wackiness is likely to crop up for someone at some point
<drewfustini> I suppose some optionality would make sense
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