sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<meowray> looks like MIPS and Codethink are adding big-endian. sigh
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<jrtc27> meowray: codethink are just doing it because of products existing
<jrtc27> but yeah
<jrtc27> sad
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