sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<sorear> What would "enabled" mean? Like using Zba/Zicond instructions in the kernel binary? Can't you already do that?
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<dramforever[m]1> <sorear> What would "enabled" mean? Like using Zba/Zicond instructions in the kernel binary? Can't you already do that?
<dramforever[m]1> really? i never saw how to do that
<dramforever[m]1> other than adding CFLAGS manually which i suppose could work
<dramforever[m]1> oh, i mean e.g. compiling all code with like zba_zbb_zicond enabled
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