Tartarus changed the topic of #u-boot to: SOURCE MOVED TO https://source.denx.de/u-boot/u-boot.git / U-Boot v2025.07, v2025.10-rc2 are OUT / Merge Window is CLOSED, next branch is OPEN / Release v2025.10 is scheduled for 06 October 2025 / Channel archives at https://libera.irclog.whitequark.org/u-boot
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<rfs613> marex: just FYI, even with u-boot-spl.bin reduced to 45kB (well below the 60kB SPL limit on CV) I'm still seeing the "SDRAM calibration failed."
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<rfs613> I'm now comparing debug prints within sequencer.c, and seeing some differences...
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<rfs613> ... and if I enable too much debug prints, the watchdog timer triggers, ugh.. ;-)
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<marex> rfs613: oh yes, that DRAM init code, that is a gift that keeps on giving
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<rfs613> marex: hehe yeah, seems so. At least I have some clues to chase now ;-
<marex> rfs613: what DRAM are you bringing up , DDR2 or DDR3 ?
<rfs613> if the debug message is correct, it's DDR3
<marex> that's what most CV/AV designs use, so should be ok
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<rfs613> so its failing in rw_mgr_mem_calibrate_read_test_patterns(), specifically on the line
<rfs613> base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
<rfs613> working version reads back 0x100 and failing version reads 0x1aa... which then causes vastly differnet code execution paths.
<rfs613> so next step is to find out why that register differs... but I guess that's a job for next week ;-)
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<marex> rfs613: tuning failure I suspect
<marex> rfs613: check clock settings (that is I think in arch/arm/mach-socfpga) , they might be wrong
<marex> rfs613: is this new board or existing one ?
<rfs613> marex: old one, just trying to bring up a newer u-boot
<rfs613> marex: I did a quick check of clocks already, but a closer look may be in order
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