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<marex>
dujem: you might want to check if that reserved-memory node gets carved out of U-Boot view of DRAM in the first place
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<dujem>
looks like ill be "borrowing" another function from mach-snapdragon
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<marex>
dujem: check for generic implementation, or add it if its still missing
<dujem>
marex: nevermind that. it seems that whenever these first 16M are touched in any way everything breaks, even if its just to mark that region as PTE_TYPE_FAULT
<marex>
dujem: maybe there is some prior stage bootloader that configures some MMU tables to protect that region ?
<dujem>
there is a 1st stage bootloader, but i do not have its source code nor any idea what exactly it does
<dujem>
the closest thing i have is an ancient u boot fork for a sbc based on the same soc
<dujem>
s/a/an
<marex>
dujem: is this arm32 or arm64 ?
<dujem>
arm64
<marex>
stick this somewhere into your misc init or arch init or somewhere where it will get called
<marex>
printf("EL: %d\n", current_el());
<marex>
what does it print ... EL2 I guess ?
<dujem>
indeed
<marex>
so probably the prior stage bootloader configured some protection on this area
<dujem>
in that case i guess it is best to do memory@1000000?
<marex>
dujem: memory@0 which describes 1 GiB of DRAM + reserved-memory to eliminate the inaccessible bit
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<dujem>
that just breaks boot completely
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<dujem>
also tried mmu_change_region_attr(0, 0x1000000, PTE_TYPE_FAULT); in dram_init() just before fdtdec_setup_mem_size_base(), doesnt change anything
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<dujem>
hm, i moved that call to a new enable_caches() and now it prints 'PTE 000000003fff0000 (0) for addr=0 should be a table', might be getting somewhere
<marex>
if you are configuring MMU, that has to happen before cache config , because cachable regions are described in MMU tables
<dujem>
wow, i finally got it working
<dujem>
turns out i had to change CFG_SYS_SDRAM_BASE from 1000000 to 0
<dujem>
now i could see is it maybe possible to access that region after all