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<isabella>
in an elf file is the physical address in phdr always ignored?
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<isabella>
or rather, in what cases is it not zero nor the same value as the virtual address?
<isabella>
like in that case what am i supposed to do with it when loading it
<EmanueleDavalli>
it's useless in all the normal cases
<EmanueleDavalli>
I don't think it's ever used
<heat>
yeah it's not useful for the OS's elf loader
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<zid>
paddr is only in sections afaik?
<zid>
Which makes it a thing you don't even look at
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<heat>
paddr is also in program headers
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<zid>
I thought that was LMA
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<ZetItUp>
isabella: you ignores paddr if you have a virtual memory system
<ZetItUp>
it's only there to tell you where to put it if you don't have one
<ZetItUp>
aka you can ignore it :D
<isabella>
ah i see
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<Ermine>
still not sure what PHY means when applied to e.g. ethernet devices. Is it the port itself?
<pog>
it's the circuit that translates the physical to the MII i think
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<pog>
so it could be twisted pair, fiber, whatever
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<pog>
even radio???
<Ermine>
so it's in between the cpu and the port?
<pog>
it's in between the port and the MAC
<Ermine>
huh.
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<heat>
its between the linux and the kernel
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<pog>
there is nothing between the linux and the kernnal
<pog>
they are one
<pog>
like the father the son and the holy ghost
<pog>
only not a trinity
<pog>
a duality
<heat>
in the name of the linus and of the linux and of the kernal, amen
<zid>
PHY is an abbreviation for the physical layer of the OSI model and refers to the circuitry required to implement physical layer functions.
<zid>
just replace 'phy' with 'port' and you're pretty much fine
<pog>
it's more than that tho
<pog>
i know for ethernet it barely matters
<pog>
but i want to be detailed and technical
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<heat>
i feel like restarting my work on hugetlb
<heat>
i was in the middle of implementing netlink but i can commit that to my ongoing-work-branch
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<zid>
pog: It's not like people don't call fibrechannel holes ports
<zid>
or spdif or whatever else
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<pog>
the technical term for them is holes
<zid>
not ussys?
<zid>
ethernussy
<kof673>
luminiferous aethernet
<pog>
the PHY of the universe
<kof673>
the dove was female it was a mystery of the father appearing as female :D phoenix comes later :D
<kof673>
two vultures lol
<heat>
pog pog pog pog po gp og pog pog pog
<pog>
heat
<heat>
bazinga
<pog>
bazinga
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<heat>
you can't out-bazinga the bazinger
<heat>
the bazingee
<pog>
i would be the bazingee because i got bazinged
<zid>
You can both go off somewhere and die
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<ZetItUp>
spent half the day trying to figure out a way to make programs able to run in kernel space if needed to, it just hit me, why would i allow a program to run in kernel space..
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<CuteMath>
Questions: on amd64 is the interrupt 32-255 enough? I've managed to get something to work (though far from usable) with HPET, AHCI and XHCI. HPET can have one interrupt per timer. AHCI and XHCI allow multiple interrupts to be assigned. Won't I run out of interrupts? In my toy OS I can assign the same interrupt to different thing by using a linked list of functions. Is that the correct way to do this sort of stuff?
<CuteMath>
Should I try to be somehow smart and balance the amount of functions I assign per interrupt?
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<pog>
if you're on linux you can see how it splits up available irqs by reading /proc/interrupts
<pog>
i have 55 irqs in use
<EmanueleDavalli>
I have 12 for the nvme controller, wow
<pog>
i have 26
<pog>
with two nvme ssds installed
<CuteMath>
not sure how to read it, each line is an interrupt slot?
<pog>
anyhow i think you're gonna be hard pressed to use 223 irqs on any ordinary system
<CuteMath>
hard to read with 32 cores lol
<pog>
each numbered line is a slot in the IDT
<pog>
a slot in the IDT that isn't an CPU-internal interrupt *
<pog>
we're well past the days of the 8192 and shared interrupts
<pog>
allocate freely imo
<CuteMath>
do I just panic in that far case?
<CuteMath>
extreme*
<zid>
8192? isn't that a realtek card? :P
<heat>
No
<heat>
Ok so the deal with linux is that MSIs are per-cpu AFAIK
<heat>
Which is the only way to handle certain hw
<EmanueleDavalli>
You *can* handle multiple devices per interrupts
<EmanueleDavalli>
*interrupt
<heat>
Some fancy NICs require some hundreds of MSI-X vectors
<zid>
100gigE kind of rough on the whole interrupts front
<zid>
when each packet is like, 100 bytes
<zid>
easier to dedicate some cores to just spin on the packet list :P
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<pog>
aha ok so you have even more than 223 vectors available
<pog>
depending how you split them between cpus
<CuteMath>
wait, isn't there just one IDT?
<heat>
Why does that matter?
<pog>
each logical cpu can have its own idt
<heat>
And no, not necessarily
<CuteMath>
oh mutiple IDTs, I see
<CuteMath>
mutiple*
<CuteMath>
I give up
<CuteMath>
lol
<pog>
the ioapic can route to whatever lapic
<heat>
As long as you assign some range statically as "this is MSI", only the actual handler tables need to be cpu
<heat>
be percpu I mean
<CuteMath>
so, when the interrupt rountine gets called, first thing to do is check on which core we are?
<CuteMath>
what would be a reasonable range for MSI?
<CuteMath>
The MSI Multiple Message Enable is 3 bits
<CuteMath>
7? seems wrong to mwe
<CuteMath>
me*
<pog>
i don't think the ISR needs to really be aware what cpu it's on
<CuteMath>
I think I see why
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<CuteMath>
got it, thank you guys
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<EmanueleDavalli>
of the ssl libraries supported by curl, which is the easiest to port?
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<zid>
I think that's pretty much like asking which is the best herpes
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<pog>
i like simplex b
<zid>
is that the same as hsv-2
<zid>
cytomegalovirus for me anyway
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<Ermine>
EmanueleDavalli: either mbedtls or bearssl
<Ermine>
first one is maintained, and second one isn't
<EmanueleDavalli>
thanks
<heat>
pog: CuteMath: if you do per-cpu MSI-X vectors then you do need to be aware of what CPU you're on
<heat>
but really, this is kind of optional
<heat>
i don't know how OSes in general do this
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<heat>
but my own OS does not bother
<heat>
as long as you don't get an mlx5 NIC or an ixgbe fancy-ass NIC or two NVMe drives in a 100-CPU system, you're fine
<heat>
and most devices don't even need MSI mode, so your NVMe storage will just be a bit slower
<heat>
it is what it is
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<isabella>
i have a question about cores
<isabella>
i wrote a simple program that calls abort
<isabella>
in the phdr i can see the value i expected in p_memsz, but p_filesz is 0. the map itself would also be larger than my core
<isabella>
this is the only executable map in glibc so i have definitely at least touched it by entering main and calling abort
<isabella>
why is it not in the core?
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<isabella>
i see, it's not dumped because it's file backed private and not modifed
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<heat>
linux has a coredump filter functionality
<heat>
which controls whether regions are dumped or not
<heat>
in general for ELF files you want to dump the first page (yes, there's a filter for this) because that allows you to grab the build-id and then you're able to match the mapping to the executable very easily
<clever>
another related thing that may help, or may be entirely useless:
<clever>
i added core-dump support to this emulator, but since its emulating an entire machine, there isnt really one elf as a base, it starts with a kernel .bin file
<clever>
so it doesnt have a base elf, it just dumps all of the ram, and throws some section headers in to point to where the kernel/dtb initial lived
<isabella>
nice
<heat>
i have actual proper coredump code on my kernel
<heat>
if you care about the logistics
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<nikolar>
how well does it work
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<heat>
pretty darn well
<heat>
i'm just missing proper xsave dump support, which i need to take of Eventually
<heat>
take care of*
<nikolar>
eventually (tm) is the best
<heat>
it's annoying because xsave layout is CPU-dependent and is encoded in cpuid
<heat>
and it's something i've been able to avoid until now
<heat>
(i still _kind of_ can because normal codegen doesn't use AVX, so just SSE works)
<clever>
if the cpu is only ever loading and saving its own state, then all you really care about is size, but yeah, once you coredump, you need to decode that mess
<zid>
dump it as hex bytes :P
<zid>
TOOOL(tm) can sort ito ut
<nikolar>
just don't compile stuff with avx :P
<nikolar>
sse only
<heat>
clever: generally yes unless you need to preload xstate values
<clever>
heat: couldnt you just load it into a float register the normal way, and then xsave them all?
<heat>
that sounds harder :)
<heat>
and will accidentally leak xstate data if you didn't intend to copy it all (e.g execve)
<heat>
a funny bit about xsave is that it's also used for new !SIMD features (like protection keys for instance)
<clever>
for execve, i would just bzero all of the saved state, then populate a few things like the initial pc and sp, and "restore" into that thread
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