sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<shadows> I've updated the Debian 13 Trixie install guide of JH7110 CPU boards (namely VisionFive2, Star64, Mars) https://wiki.debian.org/InstallingDebianOn/StarFive/VisionFiveV1
<shadows> sigh... wrong pastebuffer. should be...
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<la_mettrie> do VisionFive2 & Star64 have identical freqs in clocks?
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<palmer> I’m here this week, I’m just wandering off to find some coffee
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<bjdooks> I'm getting a bit of a weird issue, not sure if it is my latest big-endian build or if gcc15.1 isn't building the kenrel
<bjdooks> however very early on, getting a page fault and it turns out the page mapping for the fault handler doesn't exist either
<bjdooks> thus sitting in a fault loop
<bjdooks> hmm, think i've messed up my qemu tree somehow
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<bjdooks> weird, for le this works, but for be in relocate_enable_mmu: the trampoline_pg_dir doesn't have an identity mapping for the dram we are in
<bjdooks> so as soon as the satp is written, qemu fails due to the instruction area not being writable
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<bjdooks> ok, it isn't the trampoline_pg_dir
* bjdooks is begining to think uboot messed up changing the dtb and hsa given the setup_vm() code a headache
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<bjdooks> Using the stvec to jump into the trampoline pgtable is just evil
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<palmer> bjdooks: ya, and I think the code doesn’t even work right under some non-identity mapped cases
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