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<avg_surfman>
Hi, could someone tell me where the freenode risc-v IRC migrated to?
<dramforever[m]1>
here
<dramforever[m]1>
afaict
<avg_surfman>
Oh okay. Thanks. I thought there would be more people in here :/
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<avg_surfman>
How is the priviliged ISA implemented, generally? I know how a basic RISC-V pipeline looks like (https://github.com/RISC-KC/basic_rv32s) but I can't find any HDL code examples on the web
<avg_surfman>
For example the vector instructions
<avg_surfman>
are they implemented within a CPU or is it a separate logic block
<avg_surfman>
(hopefully my question isn't stupid)
<dramforever[m]1>
vector instructions is not an example of privileged isa
<avg_surfman>
sorry mb I meant the H/Virtualization extension
<dramforever[m]1>
usually inside the cpu
<dramforever[m]1>
they change the behavior of instructions so there's really no reason to put them outside
<avg_surfman>
Ah okay thanks
<dramforever[m]1>
some parts can be outside, like interrupt stuff
<avg_surfman>
What about the Vector instructions? Now that I fumbled I might as well ask :)
<dramforever[m]1>
vector stuff have like separate state registers right? so they can be a coprocessor outside
<dramforever[m]1>
although it still would be fairly integrated
<dramforever[m]1>
tightly integrated i mean
<dramforever[m]1>
you can also implement it inside
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