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<asjackson>
hmm i realised last night that i should send the extra gpib contorl signals using extra bits in the fifo, rather than via registers, since the register value might change when the queue hasn't finished writing data. so, im going to fix that today
<whitequark[cis]>
yes, registers are not synchronized with the main command stream
<whitequark[cis]>
(their interface is also kind of really awkward, though i should be able to fix that soonish)
<asjackson>
:) im still a noob
<whitequark[cis]>
I would say this is a design issue, actually
<whitequark[cis]>
a good interface would funnel you towards the appropriate solution rather than requiring niche knowledge to decide
<whitequark[cis]>
I DM'd you on IRC re: adapter boards
<whitequark[cis]>
not sure that went through
<asjackson>
huh i didnt get that!
<whitequark[cis]>
try messaging me?
<asjackson>
just sent ping
<asjackson>
i think what i thought i wanted when i was writing this was a second fifo stream for control, because i naively assumed that the fifo was 8 bits. i think it's a documentation problem, amaranth docs are awesome but it's hard to see sometimes how they apply to the glasgow. id love to help with this, i just dont know where to start
<asjackson>
im on discord too if that's easier?
<whitequark[cis]>
the FIFO is in fact 8 bits
<whitequark[cis]>
* 8 bits wide
<asjackson>
OH
<asjackson>
what happens when you push something sixteen bits wide then?
<whitequark[cis]>
re: docs, I agree that glasgow docs are lacking. I've hesistated writing lots of documentation because many of the glasgow interfaces are kind of awful and I see fixing them as more of a priority
<whitequark[cis]>
if you do something like in_fifo.data.eq(0xffff) the high bits are simply truncated
<asjackson>
completely fair
<asjackson>
docs are also a huge amount of effort
<asjackson>
ah right
<whitequark[cis]>
it's one of the few gotchas in Amaranth that are currently not in any way diagnosed by the system
<asjackson>
so i need to interleave the data?
<whitequark[cis]>
yes, you need to implement a protocol parser/serializer
<asjackson>
ok cool, i might be able to do that 😅
<whitequark[cis]>
the one I wrote for ARM7TDMI (see my last PR) could be a good inspiration
<asjackson>
awesome thanks
<whitequark[cis]>
it also shows how to use a more modern interface for FIFOs (streams rather than the obsolete one Glasgow uses)
<whitequark[cis]>
so one thing I notice about your applet is that it's pretty simple
<whitequark[cis]>
when I looked at the IEEE GPIB spec, I was completely overwhelmed, it's a monstrosity that serves more to confuse than to explain
<whitequark[cis]>
the way they describe each of the 8 data bus bits as an individual asynchronous message passing channel is completely delirious
<asjackson>
yeah there are a tonne of things which almost nothing needs, but the handshaking is the core part
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<galibert[m]>
So, an IEEE spec?
<whitequark[cis]>
some of them are worse than others
<whitequark[cis]>
the GPIB one is probably the worst
<whitequark[cis]>
like, Ethernet is a pretty chill read
<galibert[m]>
Wow, must be something
<asjackson>
as long as the additional lines are accessible, and the logic is there for sending and receiving bytes correctly, it's extensible to any other protocol on that bus (i think)
<asjackson>
i started fiddling with a gpib hp floppy drive last night.... although im not sure i can be bothered figuring out the amigo protocol
<galibert[m]>
I'd be curious to know what runs on the floppy controller side
<galibert[m]>
is it a mcu with a wd or upd chip, so something insane?