<whitequark[cis]>
I had to get ETW for Windows and Netmon with USB parsers out
<whitequark[cis]>
turns out Windows sends a Set Interface request (that crashes the device before FPGA is configured) on configuration, while Linux only does this when you claim the interface
Foxyloxy has quit [Read error: Connection reset by peer]
Foxyloxy has joined #glasgow
<whitequark[cis]>
zyp: so... i'm thinking i should implement SWO support in Glasgow
<whitequark[cis]>
it looks like there's going to be a nontrivial amount of overlap between orbtrace and glasgow
zyp[m] has joined #glasgow
<zyp[m]>
sounds like it
<whitequark[cis]>
if i export SWO data via a socket, orbuculum can consume it, right?
<zyp[m]>
yes
<whitequark[cis]>
i should do that then
<whitequark[cis]>
i've never actually looked at orbuculum, it seems neat from the landing page
<whitequark[cis]>
(i've also never used SWO)
<whitequark[cis]>
but beyond that, i think this is a good opportunity to advance some things in Amaranth; stream-related stuff is one, but i'm also thinking about implementing a HyperRAM controller for Glasgow
<whitequark[cis]>
it looks like you're using the LiteX one, so that's something you could get rid of
galibert[m] has joined #glasgow
<galibert[m]>
Is there a timeline for the HyperRAM extension?
<whitequark[cis]>
gateware or hardware?
<galibert[m]>
hardware
<whitequark[cis]>
it's not up to me
<galibert[m]>
I don't have to skills to build one myself
<galibert[m]>
Yeah, but you could have heard
<whitequark[cis]>
i think you might be able to pay JLCPCB or something
<whitequark[cis]>
lemme check
<galibert[m]>
Given I have no urgency I'd rather pay 1bitsquared
<zyp[m]>
whitequark[cis]: I've been meaning to switch to the luna one
<whitequark[cis]>
i'd like to upstream the one i'm developing for glasgow
<zyp[m]>
orbtrace is designed to make use of DDRX2 primitives to run the hyperram at 200MHz
<whitequark[cis]>
oh, i see
<zyp[m]>
as well as reusing the DQS primitives in the FPGA to handle the data strobe
<zyp[m]>
the litex implementation doesn't make use of that, relies on phase shifted PLL outputs instead, but the luna implementation does
<whitequark[cis]>
the design i'd like to build would rely on a (much improved version of) IOStreamer
<whitequark[cis]>
so the controller would form x waveform samples per cycle, the device-independent part would handle backpressure and latency, and the device-dependent part would handle instantiating the buffers
<whitequark[cis]>
but i don't know if this generic design is flexible enough for what you want
<_whitenotifier-5>
[glasgow] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-866-80fe431d3096b1516e53df14ecb8cd1d9f22303b - https://github.com/GlasgowEmbedded/glasgow
vk2seb[m] has joined #glasgow
<vk2seb[m]>
Its very similar. The main changes are A) to fix some timings bugs to do with the byte select lines and B) refactor the core so that it can work with both HyperRAM and pin-compatible oSPI-RAM
<vk2seb[m]>
It can run at full speed in both scenarios, so 200MHz is good but also 240MHz with timing violations (480Mbyte/sec)
<zyp[m]>
which memory chips are you using that's rated for 240 MHz?
ar has joined #glasgow
<vk2seb[m]>
It's not rated for that but I tested it to that speed before the memtest started failing:D
<zyp[m]>
fair enough :)
<vk2seb[m]>
APS256XXN. It also has a 16-bit mode for 800Mbyte/sec (which I'm not using)
stary[m] has quit [Quit: Idle timeout reached: 172800s]
miek__[m] has quit [Quit: Idle timeout reached: 172800s]
benny2366[m] has quit [Quit: Idle timeout reached: 172800s]
fridtjof[m] has quit [Quit: Idle timeout reached: 172800s]
GNUmoon has quit [Remote host closed the connection]
GNUmoon has joined #glasgow
altracer[m] has joined #glasgow
<altracer[m]>
and that ends up cheaper and easier than DDR3L-1066 bank of 16-bit DRAM which is good for 2Gbyte/s? Or there's a PHY reason?
<vk2seb[m]>
For my use case I had to fit everything in 2x2cm, so 8-bit bus was necessary for routing reasons. Probably LPC-DRAM would serve similar constraints well
<vk2seb[m]>
Sorry RPC not LPC, I am remembering the acronym wrong
Foxyloxy has quit [Read error: Connection reset by peer]
Foxyloxy has joined #glasgow
redstarcomrade has joined #glasgow
redstarcomrade has joined #glasgow
redstarcomrade has quit [Changing host]
ali_as has quit [Remote host closed the connection]