<whitequark[cis]>
it's only a problem in some cases
<whitequark[cis]>
if you wrote your own applet from scratch you wouldn't see it
<asjackson>
so i am learning about ffsynchronizers, very new to me, i think i get it, but if i understand it right i would need one for each .i and .o ? oe is maybe already sync? not sure 🤯
<whitequark[cis]>
for .i only
<asjackson>
oh really, so i use a comb for .o
<whitequark[cis]>
o and oe are driven by your logic, not sampled, so it does not matter (although the device on the other end would usually need a synchronizer)
<whitequark[cis]>
basically, listening is more complex than talking
<asjackson>
ah i see
<asjackson>
i was searching github and thinking "why are the output lines never using ffsync" haha
<asjackson>
im really enjoying amaranth / glasgow, thanks for your help!
<whitequark[cis]>
you can skip the synchronizer when you know that the interface doesn't do anything unless clocked and you control the clock and you know the phase relationship between your clock edge and the response of the device
<whitequark[cis]>
i'm glad you like it!
<whitequark[cis]>
i put in a lot of effort to make it accessible to novices
<asjackson>
verilog looked scary but always seemed interesting, good middle ground :)
<whitequark[cis]>
verilog is just... not a very good language. like, almost anything you would use (that isn't a thin wrapper around verilog) is better
<whitequark[cis]>
amaranth is just one choice, a fairly safe and boring one at that
<asjackson>
safe, boring and easy to get started works for me
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<asjackson>
hmm i tried swapping to data.StructLayout and im very confused that it doesn't seem to be assigning the values. i tried in amaranth/play and it should work 😱
<whitequark[cis]>
that looks correct at the first glance
<whitequark[cis]>
oh, I think I know what might be happening
<whitequark[cis]>
hm, no, your bit order is also right
<whitequark[cis]>
what are the symptoms?
<asjackson>
it's as if it's not even setting the signal when I do `m.d.sync += l_control.eq(self.out_fifo.r_data)`
<asjackson>
so it just gets stuck, since none of the conditions below that match 0
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<asjackson>
and when i change back to what i was doing before (commented out) , it works , mystery!
<whitequark[cis]>
so, there are a few ways to proceed here (I still don't see it from reading the code)
<whitequark[cis]>
if you were building the applet using the new style (wiring.Component based), you could just simulate the entire applet
<asjackson>
i was planning to do things incrementally and hopefully switch to newer style later, think it might be helpful to learn it progressively , but may be wrong haha
<whitequark[cis]>
oh, a few code style comments
<whitequark[cis]>
the amaranth.lib.* submodules are intended to be imported as the submodule itself (like from amaranth.lib import enum, data, cdc, wiring) and then referenced with the submodule name being the namespace for its contents (like wiring.connect, cdc.FFSynchronizer, enum.Enum). this helps reduce the amount of global identifiers being pulled in while also reducing import clutter
<whitequark[cis]>
(and without using glob imports, from x import *)
<whitequark[cis]>
also the usual python code style is 2 empty lines between top-level declarations like class foo: (anything that goes on the lowest indent level)
<whitequark[cis]>
but these are minor
<asjackson>
nice, will keep that in mind :) thanks
<whitequark[cis]>
re: "new style", the fact that it makes simulations much easier to do is one of the major reasons why we're doing it. ideally, in a few months, all applets will be using that style and simulating an applet would be as easy as two lines of code
<whitequark[cis]>
we're almost there, but not quite
<asjackson>
will that help with testing too? I thought it would be kind of interesting for the tests to simulate two of the applets and wire them together for bidirectional tests
<whitequark[cis]>
the ARM7TDMI PR introduces a JTAG probe tested against a JTAG TAP in this exact manner
<whitequark[cis]>
you could wire two copies of your applet together in a test just like that