<bslsk05>
​osservatorionessuno.org: A deep dive into Cellebrite: Android support as of February 2025 - Osservatorio Nessuno
<nikolar>
lol
<kof673>
nikolar :D </me points at bslsk05> [...] Eastern Serbia. The rotting corpse of this being is said to send forth each Spring a swarm of Golubatz flies
<kof673>
you will have to play final fantasy 4 for the rest of the story lol
<Ameisen>
geist: I suspect that I can do similar. I can probably reuse the chunking framework of the recompiler itself, but use that for regenerating chunks of 'microcode' instead.
<Ameisen>
that should handle self-modifying code and the like.
<Ameisen>
I use the native MIPS functionality for that - SYNCI, SYNC, and hazard barriers
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<zid>
I wish this wind would go away, a neighbour has bought some horrible wooden windchimes
<zid>
It sounds like a comedy troupe performing "Ninja infiltration goes very wrong"
<GeDaMo>
I don't like windchimes :|
<zid>
You'd hate these ones
<zid>
because I don't mind windchimes and I think they're godawful
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<nikolar>
throw rocks at the thing until it breaks
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<zid>
I might sneak over and tape it still at some point
<zid>
Hoping they notice a week later that it hasn't been making much noise lately
<zid>
then check on it and be all wtf
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<nikolar>
kek
<GeDaMo>
I just hit an age check on Reddit :|
<nikolar>
lol
<mjg>
you have an account on reddit?
<mjg>
bigger looser signal than irc!
<GeDaMo>
I'm not logged in
<GeDaMo>
It's because I'm in the UK
<zid>
yea terfs are winning whatever war they're having
<zid>
it hasn't done it to me.. yet?
<heat>
mjg: loser
<GeDaMo>
It's a story on /r/gaming about itch.io removing NSFW games
<heat>
also it's spelled loser
<zid>
My account is old enough to do porn by itself though so maybe? :P
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<sortiecat>
Another day building a gcc
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<sortiecat>
You know it's osdev when you have nightly jobs set up that build gcc about 10 times each night
<ZetItUp>
well thats 2 hours im never getting back, had a ELF file verification check in the bootloader when i used an ELF file for test, then i switched to load a raw binary, i didn't understand why it couldn't jump into the kernel, i saw the ELF verification and was like "It needs to be there", 2 hours later it was like a light went off ..
<ZetItUp>
i blame the heat
<heat>
my bad bro
<sortiecat>
heat needs to apologize
<ZetItUp>
lol :D
<sortiecat>
i propose heat spend two hours having fun playing video games to pay back ZetItUp for the time loss
<sortiecat>
I finally figured out why manual pages weren't working on my laptop, turns out I had built a custom man and put it in my path
<ZetItUp>
blame heat ;)
<sortiecat>
if ( kill(zombie, SIGKILL) < 0 )
<sortiecat>
err(1, "kill zombie");
<sortiecat>
this is currently the code I am writing with a straight face
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<nikolar>
sortiecat: how do we know your face is straight
<mjg>
:)
<mjg>
sortiecat: wtf is that about
<heat>
os-test
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<mjg>
i would not think to test that sucker, but makes sense
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<ZetItUp>
Hulk Hogan died, damn now i feel old
<pog>
i haven't watched wrestling since they split raw and smackdown into set rosters
<pog>
wcw acquisition made for hot storylines but it changed the whole thing fundamentally
<pog>
the N64 No Mercy game was peak
<mjg>
wrestling?
<mjg>
thunder in the paradise
<mjg>
or whatever the title
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<kof673>
all roads lead to cow tools lol > Tatanka from the Royal Rumble SNES video game manual
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<Ameisen>
geist: does/did arm not have instructions or a way to signal invalidation of the instruction cache?
<geist>
via instructions, yes
<Ameisen>
I'm currently using them for that since it seems sensible - `SYNCI` to invalidate an instruction cache line (that just triggers the relevant chunks to be marked as invalidated, and for the same address range to be copied to shadow memory), SYNC to flush that, and then the hazard barrier to complete it.
<Ameisen>
though SYNC and HB are basically identical to me... haven't figured out the best way to handle needing both.
<Ameisen>
it's not an asynchronous operation for me
<Ameisen>
though MIPS gets weirdly complicated when it comes to the cache. It gives you a lot of control over it, probably because the specification fully allows for memory ranges to be non-coherent.
<Ameisen>
though I have just realized I have an error in my logic... delay branches with hazard barriers clear it after the delay slot.
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<Ermine>
Surprisingly enough, mainline kernel's TEE subsystem doesn't support Trusty
<heat>
ok so now i'm going to use you as a rubber ducky
<heat>
basically, the gist of it is that the kernel crashes (but only on curl builds?) under high load. a backtrace of all CPUs indicates one or two CPUs seem to have busted stacks, weird page faults, weird KASAN problems
<heat>
i'm thinking this can be a page UaF (i'm currently not quarantining pages on a free)
<heat>
i've tried not freeing stacks at all
<heat>
(doesn't help)
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<heat>
i can't repro if i disable the stack cache
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<Ameisen>
I really hate implementing delay branches.
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<TehBoss>
i'm following the barebones tutorial on nixos, but i'm struggling to install gcc
<TehBoss>
i tried putting `pkgsCross.i686-embedded.buildPackages.gcc` in my flake.nix but it had compilation issues
<TehBoss>
ok seems like it may be a disk space issue
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<Ameisen>
So... I wanted to confirm something that's been confusing me a bit. In MIPS, as far as I know, SYNCI marks an instruction cache line as invalidated. SYNC (with GINV), aside from acting as a barrier for loads/stores, also acts as a global barrier for SYNCI instructions - basically guaranteeing that all processors see the invalidations. Then the hazard barrier jump/instruction acts as guaranteeing that the invalidation is actually completed?
<Ameisen>
I'm trying to map what the instructions do to what the VM needs to do in a sane way.
<Ameisen>
More precisely, I'm trying to figure out if the actual invalidation - resetting/updating chunks and copying to shadow memory - should happen during `SYNC` or during a hazard barrier instruction.
<Ameisen>
or are the hazard barriers just intended to flush the pipeline so that the pipeline isn't potentially executing now-invalidated instructions?
<Ameisen>
"JALR.HB implements a software barrier that resolves all execution and instruction hazards created by Coprocessor 0 state change"
<Ameisen>
based on my reading elsewhere in the spec... I believe that the barriers are more specific to the pipeline? In many cases `SYNC` is specified as having completed the invalidations upon it being retired.