sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<Abstract-Wizard> just found out about the milk-v titan and im kind of excited
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<shadows> "Open Source in the Soul" from the vendor that did faff-all to upstream all products to date.
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<ganboing> They are board integrator, not even SoC vendor, so don't put too much hope on the upstreaming effort.
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<dramforever[m]1> is it just me or is the RVI jira https://lf-riscv.atlassian.net/issues/ just not loading
<xypron> Was there any discussion at DebConf25 whether the next Debian release (14, Forky) should move to RVA23?
<dramforever[m]1> wasn't there, but i would be very surprised
<dramforever[m]1> that would be unlike how debian has worked up til now at all
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<jrtc27> it's way too soon for it to make sense to move to RVA23
<jrtc27> once there's actual hardware, sure, then have the conversation
<jrtc27> but a baseline that nothing can run is a great way to get people to not use your distro
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<dramforever[m]1> it is not a hot take that nobody else is moving on to RVA23
<dramforever[m]1> in a few years, possibly. definitely not anything recent
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<ganboing> drmpeg: sifive recently added their PMU driver for private L1/L2 and shared cache:
<ganboing> I did a perf using that with your code, and with the new prefetcher CSR values
<ganboing> The sifive_pl2_pmu/inner_prefetch_read (L1 cache prefetcher I guess), is only at 5% compared to the previous version
<ganboing> It looks like the prefetcher wasn't even working.
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<drmpeg> Have you looked at the STREAM benchmark performance in comparison?
<ganboing> Let me check. roughly, STREAM has a ~5x boost.
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<ganboing> With the new prefetcher config, sifive_pl2_pmu/inner_prefetch_read is ~9x with STREAM benchmark
<drmpeg> Woah. I wonder if there's some middle ground here.
<ganboing> I'm reading some Sifive cache docs, and trying to make sense of this. But likely Sifive/ESWIN needs to really come up with a somewhat workload agnostic setting
<ganboing> Yea.
<drmpeg> That LDPC code has an interesting history. My DVB-T2 transmitter code was used as the basis for the 2017 Rohde and Schwarz engineering competition. The winning team came up with an optimization that made the LDPC lookup table more cache friendly.
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<ganboing> Did some experiments and it seems STREAM performance can get on par with the new settings by just changing maxL1PFDist 0->2
<ganboing> It won't have very noticeable impact on your LDPC workload
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<drmpeg> Very nice.
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<Esmil> ip a
<Esmil> sorry
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<shadows> if an SDIO card (AP6256 WiFi+BT module) needs power to be detected, from configuring a GPIO pin to output high), where in devicetree is the correct place for that?
<shadows> at the moment I have it as one of the pinctrl groups listed for the mmc1 node, but I wonder if it should be power sequenced
<dramforever[m]1> shadows: do you have any specifics? right now i'm guessing mmc-pwrseq-simple
<shadows> or is power sequence not early enough for powering up an SDIO card?
<shadows> mmc-pwrseq-simple yes
<dramforever[m]1> it seems weird that a gpio is for power, are you sure it isn't reset
<dramforever[m]1> what board is this again?
<shadows> any of the JH7110 boards with AP6256 on SDIO, here it is Milk-V Mars CM Lite with WiFi option
<shadows> AP6256 is detailed on one of the last pages
<dramforever[m]1> i see it, i think it should should just be mmc-pwrseq-simple
<dramforever[m]1> it seems reasonable to treat this active-high "wifi_reg_on" as an active-low reset for power sequence purposes
<shadows> when I try instead from mmc-pwrseq-simple the mmc SDIO card is not detected
<dramforever[m]1> what properties do you have?
<dramforever[m]1> i'm thinking pinctrl-{names,0} for the pin, reset-gpios for the, well, gpio
<dramforever[m]1> sdio_pwrseq from arch/arm64/boot/dts/rockchip/rk3308-bpi-p2-pro.dts looks good
* shadows reads
<shadows> how would I add a delay to test if it just needs some time to power on?
<dramforever[m]1> post-power-on-delay-ms possibly?
<dramforever[m]1> Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml
<shadows> btw am not near my dev workflow until +6hrs I will try then and share details
<dramforever[m]1> sure, i literally do not have the hardware and just babbling :P
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<shadows> and
<shadows> (disregast line)
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